October 18th | Tektronix Cloud Lecture - Design and Verification of High-Speed Signals Such as LVDS in Signal Chains
As data rates in electronic systems continue to increase, high-speed signal chain design becomes a critical link to ensure system performance and reliability. Jitter, eye diagrams, and inter-symbol interference (ISI) are common challenges in high-speed signal transmission, which directly affect signal integrity and thus increase system bit error rates.
This live broadcast will give you an in-depth understanding of the core elements of high-speed signal chain design, analyze the selection criteria of commonly used transmission standards such as LVDS and JESD204B , and explore how to optimize signal transmission through equalization technology, reduce system bit error rate, and thus improve the overall performance of the design .
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October 18, 2024 (Friday) 14:30-15:30
Lecturer Introduction
Yu Yang
Technical Manager of East China
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