Thermal management design using discrete semiconductor devices

Reprinted from All About Circuits official website, author Toshiaki Hosoya

There are several ways to effectively improve the high-temperature issues encountered in today's discrete semiconductor designs. Simulation techniques are critical to measuring how well various methods work.

As we all know, the temperature of semiconductor chips is constantly rising. The heat it generates can cause serious problems with performance and functionality. As shown in Figure 1, there is a growing need for surface-mount packaged products that provide optimal thermal performance.

There are many approaches to thermal design that support heat dissipation, but which approach works best?

Figure 1. PKG3 is clearly the source of thermal issues in this simulation, which can be addressed with modern thermal design methods.

There are several reasons behind the rising temperatures of discrete semiconductor devices. One is the reduction in self-heat dissipation due to the reduction in the size of electronic devices; the other is the increase in ambient operating temperature due to high-density board assembly. In addition, the pursuit of higher speed operation is also accompanied by an increase in heat generation.

There are several ways to mitigate temperature problems1 ^. For example, a multi-layer PCB will affect the thermal design of electronic devices because most of the heat generated will be dispersed through thermal conduction to the top and bottom surfaces of the PCB and to the internal structure. Increasing the number of layers can effectively improve power dissipation. However, this method is only efficient when 4 to 8 layers are used, and it will also increase costs.

Installing a heat sink directly on the PCB can also dissipate the heat generated by the components on the PCB. But the amount of heat dissipated directly depends on the heat sink size and the heat sink emissivity.

Increasing the size of the radiator seems to be effective in enhancing heat dissipation, but at the same time, a balance between size and cost constraints must be considered. Surface treatment with anodized aluminum is an effective measure to improve the emissivity of the radiator, but it is also limited by cost.

使用铜布线层可显著提高电路板本身的导热性。此外，增加布线层厚度可进一步增加有效散热的表面积，从而增强电路板的整体导热性。

Thermal interference is especially noticeable when multiple heating devices are arranged in a row. If two devices are too close together, heating is a bigger problem. While spacing devices further apart can help, there are marginal effects from being too far apart. Another factor is TIM (Thermal Interference Material). Using a thinner TIM will help with more efficient heat dissipation, but its optimization will be more challenging if smaller electromagnetic wave interference is involved.

Vias are holes in a PCB used to establish electrical connections between the layers of a printed circuit board. Internal vias located under the drain frame dissipate heat very efficiently. At the same time, although blind holes are not very efficient in heat dissipation, they can well prevent heat from being conducted to the surrounding area.

Not all of the above methods are equally capable of solving heating problems, and their effectiveness can vary significantly depending on design conditions. Therefore, Toshiba conducted simulations2 ^to evaluate the effects of various thermal design methods and the parameters that produced the best results.

For more details on model and simulation details, see the application note Thermal Design Tips and Tricks for Discrete Semiconductor Devices Part ²³ . Note that one of the benefits of these simulations is the opportunity to use models and conditions that are not possible through physical measurements.

The device model used to evaluate the thermal design this time uses Toshiba's SOP Advance ⁴ , TSON Advance ⁵ , and DSOP Advance ⁶ chip packages, as shown in Figure 2 below.

Figure 2. General simulation model

The PCB is modeled as a 2 inch square and only the solder mask on the back side is modeled. The presence of solder mask on the front side is simulated by increasing the emissivity of the board material (e.g. glass epoxy FR4). This method was strategically chosen to reduce the density of the surface mesh while maintaining the same effect as solder mask.

Based on the most commonly used PCB, this PCB thickness is approximately 1.6mm. The standard PCB used in the simulation was modeled with four layers, copper was used as the wiring material, and all copper wiring thickness was set to 70μm for evaluation.

The vias are modeled as 0.25 mm square thermal vias placed on the drain routing as the primary thermal path in the package. Vias placed underneath the copper routing are modeled as internal vias; vias on the periphery are used as vias. All simulations use a heat sink modeled with the same shape cuboid, except when parameterized.

For the thermal interference model, three identical devices were placed on a common drain trace, using the same PCB dimensions as the previous single device simulation.

For all models, use the same physical property values ​​for the TIM and only use vias as its thickness. Place the TIM (1) between the copper wiring and the device and (2) between the copper wiring and the heat sink to evaluate the effectiveness of the TIM.

As shown in Figure 3, the simulation accuracy is within the acceptable range of ±5%.

Figure 3. Comparison of MOSFET measured and simulated temperatures

The effect of multi-layer PCB is shown in Figure 4. The simulation results show that when the number of PCB layers increases from 4 to 8, the chip temperature decreases by 7%. The main problem is the increased cost.

Figure 4. PCB layer number VS chip temperature

Increasing the wiring thickness from 70μm to 105μm reduced the chip temperature by 6%.

For the design without a heat sink, adding a 1cm high heat sink reduces the chip temperature by 12%. If a radiator with a height of 2cm is used for modeling, the board temperature will be reduced by 19%. This specific method is more efficient than relying solely on PCB cooling.

通过用阳极氧化铝处理表面，散热器的发射率可以从0.04增加到0.8。当实施这种散热器时，芯片温度降低了12%。虽然这种表面处理会非常有效，但显著增加了成本。

For a row of three devices, when the spacing is 3mm, the chip temperature increases by 3%; but when the spacing is 12mm, the temperature does not increase.

For smaller surface areas, it is beneficial to use a thinner TIM; but for larger surface areas, the situation is different.

Placing vias under the drain frame has proven to be very effective compared to a PCB without vias. When three vias are added, the chip temperature decreases by 9%, and when five vias are added, the chip temperature decreases by 12%.

Compared to a PCB without vias, adding six vias reduces the chip temperature by 7%, while adding ten vias reduces the chip temperature by 10%. But it's worth noting that external vias are not as effective as vias placed under the drain frame. On the other hand, using external vias does have a nice benefit: they prevent heat from conducting to the surrounding area.

Not all surface mount packages provide the same thermal design and performance, which is why Toshiba is actively developing packaging solutions that provide excellent thermal performance, including MOSFET packages7 ^, SOP Advance packages8 ^and the TO-247 used in simulations Package ⁹ .

Toshiba has semiconductor components that use advanced packaging and implement sophisticated thermal design methods. Toshiba can perform simplified thermal simulations to help you better understand the temperature distribution of your design and find effective ways to minimize temperatures. Contact them to learn how Toshiba can help solve thermal issues in your designs.

For more information, please copy the link below to visit:

1： https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00071.pdf?did=59467

2： https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00075.pdf?did=60342

3： https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00075.pdf?did=60342

4： https://toshiba-semicon-storage.com/cn/semiconductor/design-development/package/detail.SOP%20Advance.html

5： https://toshiba-semicon-storage.com/cn/semiconductor/design-development/package/detail.TSON%20Advance.html

6： https://toshiba.semicon-storage.com/ap-en/semiconductor/design-development/package/detail.DSOP%20Advance.html

7： https://toshiba-semicon-storage.com/cn/semiconductor/design-development/package/mosfet.html

8： https://toshiba-semicon-storage.com/cn/semiconductor/design-development/package/detail.SOP%20Advance.html

9： https://toshiba-semicon-storage.com/cn/semiconductor/design-development/package/detail.TO-247.html