Now, by introducing physical and scalable modeling technology, ON Semiconductor has further improved the simulation accuracy to a higher level. This article will mainly introduce the relevant content of physical and scalable simulation model functions .

This modeling technique based on physical formulas, process parameters and layout parameters takes into account all the non-linearities that our products introduce into modern power switching devices. Physical formulas capture the temperature dependence and propagation effects of modern power devices in all the different regions. A core model is created for dedicated technologies (SiC MOSFET M3 and IGBT FS4, etc.) - setting the chip size via layout parameters to obtain a specific device.

Physical and scalable simulation models contain much more than the data sheet values ​​obtained through data sheet parameters or in an almost ideal measurement environment. The model simulates all values ​​under all conditions within specification limits. Parameters or curves not provided in the data sheet can also be captured in physical and scalable simulation models - and can be obtained through simulation. Most of the time, just run a simple simulation schematic.

To illustrate the power of physical and scalable models, we will compare the output capacitance results obtained by simulating two superjunction MOSFET models: a behavioral model and a physical and scalable model. The two superjunction MOSFETs have similar performance (on-resistance of about 18mΩ at 650V). First, we overlay the simulation results with the measured data.

Figure 1. Behavioral model output capacitance simulation results

In the graphs above and below (Figures 1 and 2 respectively), the colored curves are obtained through simulation, while the overlaid black curves are based on device specifications. Figure 1 is from a competitor model because all ON Semiconductor Superjunction MOSFET models are not behavioral models but physical and scalable models. The behavioral model fails to capture the nearly 10 ³ drop in output capacitance, which is inherent to all superjunction MOSFETs.

Figure 2. Physical and scalable model output capacitance simulation results

Next, to compare the same silicon superjunction MOSFET model used to obtain Figures 1 and 2, we plotted the output capacitance (or COSS) this time using the same logarithmic scale. This scale exaggerates the difference, but helps us read the simulation results of the maximum capacitance value at the minimum blocking voltage and the minimum capacitance value at the maximum blocking voltage for both devices, as shown in Figure 3.

Figure 3. Comparison of output capacitance simulation results from behavioral model to physical and scalability model

Suppose we want to simulate a soft-switching or zero-voltage switching application using a half-bridge or full-bridge structure. During conversion, we consider the inductor current to be constant, which means the inductor is large enough.

Figure 4. Comparison of output capacitance simulation results from behavioral model to physical and scalability model

We tried to obtain almost the same conversion time (Figure 4). Since the capacitance values ​​at low voltages vary by a factor of ten (see Figure 3), the current values ​​required to charge the output capacitor and obtain soft transitions also vary by a factor of ten.

As shown in Figure 2, the output capacitance value (or COSS) given by ON Semiconductor’s physical and scalable simulation models is accurate and realistic. This means that it is also valid to simulate the current required for soft switching using the ON Semiconductor physics and scalable simulation models in Figure 4.

Using a behavioral simulation model, you will underestimate the energy required for resonant conversion by a factor of 10 - an error or error that can result in the need for a complete redesign of the application's resonant tank and system.

Now you can simulate zero-voltage switching transitions with exceptional accuracy using ON Semiconductor physics and scalable simulation models. You will get the actual energy required for the conversion because the simulation model captures all capacitive nonlinearity of C _OSS over the 10 ^3x change rate range.

Bonding and packaging are between the chip and the electrical and thermal contacts. Assembly affects chip performance through parasitic series inductance and resistance or electrical impedance and thermal impedance. Package pins plus bonding and metal masks can add up to 10mΩ of series resistance.

To quantify these effects, the internal nodes of the three-pin MOSFET, such as the gate, drain, and source, can be accessed (see Figure 5).

Figure 5. Internal nodes and external nodes

In extremely high-speed switching, the gate is the most critical signal in both hard and soft switching. It is very necessary to know when the MOSFET actually turns on and off. For example, it can help designers set the delay between the high-side and low-side switches in a half-bridge configuration.

To access internal nodes, find the device and available pin names. Pins are labeled with an "i" at the end, which means "internal."

In SIMetrix, the internal node voltages can be obtained simply by selecting this feature in the simulation options control panel. Then, the name looks like "Qn:xy:di" (for example) for the internal drain node voltage. It is directly the chip level voltage. We can now measure the actual drain-source voltage applied to the chip without any parasitic effects that might increase or decrease ringing.

We used a half-bridge architecture consisting of the SiC MOSFET NTHL015N065SC1, varied the external gate resistance, and compared the drain-source voltage difference between chip level and package level. The device is available in TO247 three-pin package.

In the image below, we can compare the drain-source waveforms at turn-on and turn-off. When on, the ringing is lower, and the opposite is true when off (see Figures 6 and 7).

The light curve is the chip drain-chip source voltage, and the dark curve is the package drain-package source pin voltage.

Figure 6. Difference in internal and external drain-source voltage during turn-on

Figure 7. Difference in internal and external drain-source voltage during shutdown

As mentioned earlier, obtaining the actual chip gate signal helps provide relevant information. We used a half-bridge architecture consisting of SiC MOSFET NTH4L015N065SC1, varied the external gate resistance, and compared the gate-source voltage difference between chip level and package level (see Figures 8 and 9).

Figure 8. Difference in internal and external gate-source voltages as a function of external gate resistance

The light curve is the chip gate voltage, while the dark curve is the package gate pin voltage.

Let's see step by step what happens when the gate resistance changes. When the resistance is greater than 10Ω, the external and internal gate voltages exceed the threshold almost simultaneously (i.e. 2V for ON Semiconductor SiC MOSFETs). There is a delay within 10ns.

When the resistance is less than or equal to 5Ω, we can see that during turn-off, only the external gate voltage will experience voltage spikes and more and more oscillations, while the internal gate voltage is relatively smooth.

When the resistance is 5Ω or 2Ω, a considerable delay (approximately 40ns) between the two voltages (external and internal) is evident at the threshold crossing .

For 5Ω, the external voltage gives a turn-off time of about 80ns, while the internal turn-off time is about 120ns, so a 50% extension. For 2Ω, the situation is even worse. The external voltage gives a turn-off time of about 40ns, while the internal turn-off time is 80ns, so the turn-off time is extended by 100%.

Depends on the ratio of external and internal gate impedance. In the Figure 8 example above, the internal gate resistance is just under 1Ω.

In Figure 9, we increased the internal gate resistance to closer to 5Ω by changing the chip design and gate flow path, but for the same package we typically see a longer off-time, as expected. At the same time, the gate network is more damped and there is less ringing on the external gate node voltage.

Figure 9. Difference in internal and external gate-source voltages when increasing internal gate resistance

Figure 9 shows that when the external gate resistance is lower than 10Ω, the delay between the internal and external gate voltages is longer. Some manufacturers use high internal gate resistance to reduce maximum drain-source dV/dt and EMI content and limit failures caused by gate oxide stress.

However, relying on an external gate voltage waveform to set the delay between switches in a half-bridge or full-bridge architecture also increases the risk of breakdown.

Figure 10. Gate-source voltage delay

When the external resistance is below 10Ω, there is a large difference in threshold crossing time, as shown in Figure 10. Even the zero-crossing and turn-off threshold crossings of the internal gate and external gate signals occur at different times. In the case of a half-bridge architecture, where the MOSFET switching phases are different or the architecture is used, we can measure the turn-off delay on the external gate to be much lower than the actual turn-off time. Therefore, it will cause the MOSFET on the other side to turn on prematurely and cause severe breakdown.

Likewise, getting the internal chip voltage is very helpful in setting the appropriate delay to avoid cross-conduction between the high and low side.

Models available online are generated and calibrated using factory nominal values. They give typical data sheet values.

However, in reality, due to process differences in manufacturing, parameter values ​​follow a Gaussian distribution.

For a specific technology, you can create a model with minimum and maximum values. We can then study the parallel connection of different devices, or see how the devices respond to extreme numerical changes.

To illustrate this performance, a high-voltage buck stage circuit consisting of three SiC MOSFETs operating in parallel is used (see Figure 11).

Figure 11. Boundary model step-down stage

Figure 12. Buck stage waveform of SiC MOSFET boundary model

The results in Figure 12 show that the current flow in the SiC MOSFET is very unbalanced. During the on-time, the current in the switch or SiC MOSFET is divided into 30A, 12A and 7A, and the average steady-state current in the inductor is 50A. The theoretical current flowing through each MOSFET is approximately 17A, with a +13/-10A error. So, in terms of current balancing, QH1 (lowest threshold MOSFET) has an error of +76%, QH0 (average threshold MOSFET) has an error of -29%, and QH2 (highest threshold MOSFET) has an error of -59%.

We can now also analyze the turn-on and turn-off details using Figures 13 and 14.

Figure 13. Partial enlargement of turn-on sequence

When turned on, as shown in Figure 13, the current flowing in the SiC MOSFET with the lowest threshold voltage is much higher. This MOSFET carries most of the inductor current as well as the reverse capacitive SiC Schottky diode current. Furthermore, not all SiC MOSFETs have the same conduction losses.

Likewise, during turn-off, almost all current flows into the SiC MOSFET with the lowest threshold voltage (see Figure 14).

We can also see that the current of the SiC MOSFET with the highest threshold voltage starts to decrease first, and then the current of the SiC MOSFET with the intermediate threshold voltage also starts to decrease. However, before the two SiC MOSFETs are completely turned off, the resonance in the tri-gate network will make the two SiC MOSFETs conduct worse because their overall gate-source voltage will increase slightly. They conduct again during the negative slope of the switch node voltage, but only for a small fraction of the total current.

Figure 14. Shutdown sequence zoomed in

Figure 15. Partial zoom of internal and external gate-source voltage turn-off sequences.

Likewise, if we analyze the difference between the internal and external gate-source voltages, we obtain the results in Figure 15. It can be seen that there is gate network oscillation in the external gate-source voltage. There is also a noticeable spike in the external gate-source voltage when the switch node voltage has a negative slope. In Figure 14, this spike can also be seen on the common drive voltage at 71.2 μs.

We can integrate the product of the drain-source voltage and the drain current to obtain the switching loss energy or the conduction loss power based on the integration period (on, off, and on time). We can also average the same product over one switching cycle to obtain the total losses for each SiC MOSFET.

Figure 16. Total power loss per SiC MOSFET

As expected and shown in Figure 16, the Si CMOSFET with the lowest threshold voltage has the greatest total losses.

Looking further, the lowest threshold SiC MOSFET has losses of just under 100W. Devices with intermediate threshold voltages lose between 38W and 39W, while the highest threshold SiC MOSFET losses range from 36W to 37W.

When we use hysteretic control or self-oscillating feedback, the switching frequency is not very stable. This results in some simulation and calculation errors per cycle. Simulation accuracy and randomly varying simulation time steps also cause errors – translating into some noise on the curves.

Figure 17. Turn-on, turn-off and conduction loss energy for each SiC MOSFET

The conduction losses during each switching cycle (see Figure 17) are consistent with the conduction current in each SiC MOSFET. This is not surprising.

Regarding the turn-on energy, the lowest threshold SiC MOSFET has an average turn-on energy of 400 μJ, which is almost double compared to the 250 μJ of the other two.

In SiC MOSFETs with the lowest threshold voltage, the turn-off energy is much higher, exceeding 550 μJ. The SiC MOSFET with an intermediate threshold voltage has a turn-off energy of 120 μJ, while the SiC MOSFET with the highest threshold voltage has a turn-off energy of only 90 μJ. One of the MOSFETs differs from the others by a factor of five.