British experts | Advances in gate driver ICs enable switching power supplies to achieve new levels of power density

Currently, the German VDE specification DIN VDE V 0884-11:2017-01 (“VDE 0884-11”) is the “gold standard” for device-level standards for electrically isolated gate driver ICs.

VDE 0884-11 is the first industry standard for any electrically isolated semiconductor product (i.e., whether optical, magnetic, or capacitive) that does not only consider isolation barrier characteristics at zero time (i.e., when the manufacturer tests the product). VDE 0884-11 also requires a product service life of 20 years. To this end, the gate driver IC is subjected to a time-dependent dielectric breakdown (TDDB) lifetime test tBD (time to breakdown), which has an upper limit of 37.5 years (see Table 1).

There are no product life requirements in the well-known device-level isolation standards (such as UL 1577, IEC 60747-5-5 or VDE 0884-10, which expires at the same time).

Since VDE 0884-11 is a German standard, it has been merged with the largely similar international IEC 60747-17 standard, which was published on September 20, 2020.

The VDE 0884-11 standard contains a very important statement that cannot be ignored:

"Safe electrical isolation can only be guaranteed within the safety class. Compliance with the safety class should be ensured by suitable protective circuits."

Table 1. Overview of device-level isolation standards

Consider the worst-case scenario in a half-bridge: the high-side MOSFET has a gate-drain short while the low-side MOSFET conducts. In this electrical overload ("EOS") condition, we can observe over 600 A of current flowing to the gate driver IC output. Therefore, to protect the gate driver IC output, we supplement the gate resistor (R1) with a suppression diode (D1) (see Figure 1). The suppression diode provides a bypass for the gate driver output, directing current to the half-bridge midpoint. Therefore, as long as we choose the appropriate application design, the isolation function of the gate driver IC from the output to the input can be maintained.

Figure 1. EOS test setup

In addition to maintaining this isolation function, bare metal covered with mold compound is often not visible, i.e., the integrity of the package must be maintained.

EOS testing has shown that gate driver ICs with an isolation barrier embedded at the IC input, such as the EiceDRIVER™ 2EDR family from Infineon Technologies AG , can meet both requirements even without suppressor diode D1.

This solution is common since a bootstrap power supply for high-side gate driver ICs is a very cost-effective solution. Therefore, half-bridges and full-bridges in high-voltage LLCs (typically 400 V DC bus voltage), or hard-switched full-bridges on the primary side of low-voltage DCDC converters (for example, 48 V to 12 V) usually have a bootstrap circuit.

The gate driver IC UVLO has a short start-up time, which provides advantages for bootstrap designs in many aspects:

Figure 2. State-of-the-art dual-channel isolated gate driver IC

U VLO startup time comparison

When UVLO-triggered output stage shutdown is reached, the main goal is to protect the switching device against thermal overload quickly enough.

At the same time, the switching stage should not be switched off if it only drops below the UVLO _off threshold intermittently.

Practical experience shows that a turn-off delay of 500 ns is a good choice to avoid noise or ringing on V _DD (caused by load jumps, for example) from causing an unintended output stage turn-off.

The purpose of the output clamp is to ensure safe shutdown of the output stage while the gate driver supply remains below the UVLO _on threshold. This reduces the risk of shoot-through during half-bridge bootstrap startup.

When the supply voltage is above the UVLO _on threshold, the gate driver IC is expected to pass the control input to the output stage, i.e. the output is no longer clamped but follows the input signal.

In the bootstrap half-bridge stage, when the low-side switch charges the boost capacitor, the capacitive voltage divider consisting of C and C of the high-side switch _causes V _to exceed _its conduction threshold. The purpose of the gate driver IC output clamp is to prevent VGS from _exceeding this conduction threshold and effectively short circuit it. If the output clamping does not occur, the high-side switch and the low-side switch are turned on at the same time, forming a half-bridge pass-through.

Advanced gate driver ICs have output clamping circuits that activate at V _DD levels as low as 1.2 V, making them ideal for "textbook" startup of high-side switches (see Figure 3).

The purpose of introducing dead time in the half-bridge is to cause the switch tail current to decay after the switch turns off but before the other side of the half-bridge turns on. Otherwise, a pass-through event may occur. Superjunction power MOSFETs such as CoolMOS™ from Infineon Technologies AG have typical decay times in the range of 300 ns.

In a normally operating system, the software running in the controller IC meets this dead time. This allows the controller IC to manage the effective duty cycle of this switching stage. The real-time performance of the controller IC hardware, operating system, and application software all play a role in determining dead time for software control. Therefore, the effective software-based dead time is usually not less than 300 ns. But in most cases, this dead time is much longer.

To prevent software-based dead-time control from malfunctioning, the gate driver IC's built-in shoot-through control and dead-time control serve as a second-level safety mechanism to prevent shoot-through events.

Modern dual-channel isolated gate driver ICs implement configurable dead-time settings via external resistors. The dead time ranges from 10 ns to 1000 ns, so there is a lot of room for choice. Therefore, this gate driver IC is ideally suited for a variety of power switching technologies, including gallium nitride (GaN) power switches . Dead time accuracy can reach +/-15%. In practice, this is often much more precise than the actual control of IC-based dead time control.

Dual-channel electrically isolated gate driver IC available in 150 mil and 300 mil DSO packages, typically in 14-pin configuration. At the gate driver IC level, the difference between the traditional 16-pin configuration and the increasingly popular 14-pin configuration is that the former "empty" pin at the output is virtually gone (Figure 4).

This enables additional PCB top routing. Alternatively, functional isolation voltages between channels up to 1025 VRMS can be achieved due to the resulting increased channel-to-channel creepage distance to 3.4 mm (referenced to IEC 60664-1, pollution class I).

The package size of electrically isolated gate driver ICs is very important, and designers now have the option of a leadless 4x4 mm2 ^package . Compared to the default 5x5 mm ² package size, the 4x4 mm ² gate driver IC saves 36% of PCB area. Input and output isolation ratings are equivalent to V _ISO =2250 V _RMS (UL 1577).

Most modern dual-channel low-side gate driver ICs have two inputs, but these are usually tied to fixed potentials, which means that the inputs are not actually used. So what is the reason for such inputs, especially when high power density is desired?

Dual-channel low-side gate driver ICs in 6-pin packages (such as pinned SOT-23 or even leadless ultra-small 1.1x1.5 mm ² 6-pin packages like TSNP) are very practical and cost-effective solution (Figure 5). In this way, all the advantages of gate driver ICs are realized, such as digital on/off characteristics, defined UVLO, 5 A strong output stage, single-digit ns propagation delay accuracy. At the same time, it minimizes PCB area occupation and improves PCB layout flexibility.

Gate driver ICs incorporate electrical isolation, a feature that has evolved from a product feature certified to be valid only in the zero-hour state to a product feature with a specified product operating life of 20 years. With proper application design, isolation functionality and package integrity are not compromised even under severe electrical overload conditions.

Shortening the UVLO startup time speeds up system startup and avoids saturation of the main power transformer. Proper UVLO turn-off time protects the switching device from thermal overload and helps ensure robust operation in the presence of VDD noise or ringing.

While the gate driver supply remains below the UVLOon threshold, the active output clamp provides a low impedance path to ground for the gate driver IC output. This most common approach avoids half-bridge shoot-through events during bootstrap startup.

The gate driver IC hardware has built-in configurable shoot-through protection and dead-time control, which are important secondary safety mechanisms. Packaging innovations have removed unused pins (formerly called “empty” pins), and package sizes are getting smaller.