IMEC discusses new progress in EUV technology

Latest update time：2019-09-04

Reads：

In 2019, EUV lithography (EUVL) will reach an important milestone. After years of waiting, advanced lithography technology has finally entered high-volume production. EUVL will be used first for the most critical metal layers and vias in the logic back-end (BEOL) at the 7nm node (imec N8 or foundry N7). At the same time, research centers are exploring options for future technology nodes that will gradually incorporate more EUVL printed structures. In the first part of this article, Stefan Decoster, R&D dry etch engineer at imec, compares the pros and cons of different multi-patterning schemes at N3 and beyond.

Compared with the past, researchers now use EUVL as an option for the patterning process of key memory structures, such as the pillar structure of DRAM and the MTJ of STT-MRAM. In the second part of this article, Murat Pak, a research engineer at IMEC, proposed several STT-MRAM key structure patterning schemes.

Introducing EUV multiple development in the back-end

This year, some major foundries will use EUVL for the first time in their high-volume production lines to process logic 7nm (N7) chips. They will introduce EUVL into the most critical metal layers of BEOL (local M0 to M3), as well as the vias that interconnect these metal layers. In these layers, the lines and trenches have a pitch of the order of 36-40nm. The trenches are separated perpendicular to each other to produce separations in continuous trenches. The next technology node, N5, will use metal pitches between 28 and 32nm.

“In 2017, we have demonstrated that these 32nm pitch lines can be patterned directly with EUVL in a single exposure,” added Stefan Decoster. “Alternatively, a hybrid option can be used, where 193i-based SAQP is combined with EUV block.”

Shown is a 32nm pitch M2 layer patterned using 193nm immersion SAQP, and blocks patterned directly by EUV.

From EUV single-shot development to EUVL multi-shot development

At the same time, it is clear that EUVL single exposure has reached its limits at 32nm to 30nm pitches. Stefan Decoster: “Beyond 30nm pitch, further scaling down will require multiple patterning techniques using current EUVL technology (i.e. 0.33 numerical aperture (NA)). These techniques typically involve splitting the chip pattern into two or more simpler masks and can exist in different flavors. EUV multiple patterning will be pushed out sooner than originally thought, mainly due to the presence of random failures. “These failures start to become more pronounced at extremely small feature sizes and limit the practical resolution of EUV single exposure.

Multiple development solutions for IMEC N5 technology node

In practice, this means that the IMEC N5 (or foundry N3) technology node has a 21nm metal pitch, which requires EUVL multi-patterning, such as SADP or LELE, of course, IMEC also offers two other schemes, namely 193iSAQP, 193i SAOP, which can still achieve these sizes of lines and trenches. Each of these technologies has its own advantages and disadvantages in terms of cost, lithography quality and process complexity.

“However, EUVL single patterning does not stop there,” Stefan Decoster clarified. “We expect that more relaxed metal layers (e.g. M4 to M7 layers) and critical vias can still be achieved with EUVL single patterning. In addition, imec and ASML are developing the next generation of high-NA EUVL systems (NA = 0.55) to further improve the resolution of single patterning.”

IMEC N5 and below: 16 nm pitch patterning solution

IMEC researchers explored four different patterning schemes for making patterns below 20nm pitch: 193i-based SAOP, EUV-based SADP, EUV-based SAQP and EUV SALELE. Stefan Decoster: "All four schemes can make lines with a 16nm pitch. However, they differ in process complexity, cost, scalability and design freedom, which are important considerations for the industry. We also found that line edge roughness (LER) remains a major concern."

193nm immersion lithography can still do the job

At these aggressive pitches, 193nm immersion lithography can only be used in combination with SAOP, starting from 128nm pitch and undergoing three pattern multiplications to finally reach 16nm pitch. Stefan Decoster pointed out that the advantage of 193i SAOP is the small line edge roughness (LER), but an inherent disadvantage is the extremely long and complex process flow, which brings challenges to process control and cost.

Using EUVL multi-patterning can shorten the flow

“For this reason, we also explored a ‘shorter’ EUVL-based patterning scheme, namely SADP with EUV”, adds Stefan Decoster. “To achieve this patterning method, the starting pitch of EUV lithography had to be 32nm. Although current EUVL technology is still able to make 32nm pitch lines, the resulting line width cannot be less than 16nm. Therefore, we had to apply additional trim techniques to achieve a line width (mandrel) of 8nm at 32nm pitch. With SADP technology, this pitch can be successfully reduced to 16nm.” Patterning with a 16nm pitch can also be achieved using the more scalable EUVL SAQP method, starting from a more relaxed 64nm pitch. However, for these EUV-based multiple patterning methods, line edge roughness (LER) remains an important issue. The team believes that this LER can be further reduced, for example by choosing the right photoresist material and improving the photoresist smoothness.

Three patterning flows enable 16nm pitch patterns (top-down SEM images): (top) EUV-based SADP, (middle) EUV-based SAQP, and (bottom) 193iSAOP. LER for all three options is measured at 8nm line and space.

eSALELE: A new process integration solution

The previous three multi-patterning methods all have one thing in common: first, lines and trenches are made, and then blocks are added (for example, using self-aligned block methods). The IMEC team also studied a different method using EUVL, called eSALELE, in which lines and blocks are defined throughout the same process. In addition to the relatively high LER, another disadvantage of this method is the use of four EUV masks (two for lines and two for blocks), which makes this solution very expensive. "But the main advantage of the eSALELE method is the design flexibility and the avoidance of 'dummy' metal lines (metal lines that are not really needed in the layout)," said Stefan Decoster. Avoiding the appearance of these lines is beneficial to reducing RC delays and back-end power consumption.

EUVL Single Exposure and Memory: The Case of STT-MRAM

Due to its high write and read speeds, STT-MRAM has recently become a possible option to replace SRAM-based last-level cache memory. The core structure of the STT-MRAM device is a pillared MTJ, in which an insulating layer is sandwiched between two thin ferromagnetic layers, which are the pinned layer and the free layer. The MTJ can exist in two different resistance states: a low resistance state (LRS, the magnetization of the two magnetic layers is parallel) and a high resistance state (HRS, the magnetization is in an anti-parallel state). Writing to the memory cell is performed by switching the magnetization of the free magnetic layer using a current injected into the magnetic tunnel junction. The read operation relies on tunnel magnetoresistance (TMR), which is a function of the resistance difference between the two resistance states.

From 193i to EUVL single exposure

So far, MTJ has been patterned with 193i to achieve a 200nm pitch, and of course 100nm pitch in the future. Murat Pak, R&D engineer at IMEC, said: "But to meet the high-density requirements of future memories, we need a tighter pitch, such as 50nm or less, with an MTJ diameter of about 20nm. 193i cannot achieve such an aggressive pitch, which highlights the need to introduce EUVL single exposure."

LCDU will be the most critical indicator

However, at such small dimensions, the impact of roughness and random failures cannot be ignored, so improved patterning schemes are needed. "For this type of memory, the most critical parameter turns out to be the local CD uniformity (LCDU), which is a measure of pillar roughness," explains Murat Pak. "This LCDU obviously affects the resistance value and thus the read performance of the STT-MRAM cell. Therefore, ensuring a good LCDU is critical for STT-MRAM manufacturing."

(Left) Shows the resistance state and the allowed range of variation; (Right) X-SEM cross-sectional image of MTJ.

Different EUV lithography schemes have been proposed and compared to optimize the LCDU of MTJs. Murat Pak: "First, we considered different photoresists, including the well-known chemically amplified resist (CAR), and two different MCR (metal-containing) photoresists. Second, our team screened different bottom layers including spin-on carbon (SOC) and spin-on glass (SOG), and studied their effects on the photoresist performance. Finally, we studied different tonalites (equivalent to the difference between positive and negative photoresists, editor's note), specifically CAR photoresists (to make pillars) and positive tone photoresists plus tone inversion processes (to turn holes into pillars). "The team also studied whether the improvement in LCDU on the photoresist would be transferred to after etching. EUV in all the above experiments was exposed using ASMLTWINSCAN NXE:3300B.

Illustration of the tone inversion process: (left) holes obtained with positive tone CAR photoresist and (right) pillars obtained after tone inversion.

Three possible solutions (as shown below, added by the editor)

One of the MCR photoresists achieved relatively good LCDU results with both SOC and SOG. The third option, a tone inversion process, also performed well. "For all three methods, we achieved more than 20% LCDU improvement," added Murat Pak. "This is an important step for the entire process flow toward the 1.55nm LCDU target." For these promising lithography process options, other performance indicators such as process window analysis, pillar roundness and size uniformity have been verified.

How to find a needle in a haystack?

How to reduce the probability of failure is crucial in the process of lithography process development. Of course, this is easy to say, but in fact there is no complete theoretical framework to predict failure so far, and failure can only be observed through direct measurement of wafers. The difficulty of failure detection lies in how to strike a balance between speed and sensitivity: speed, because a large amount of data needs to be processed; sensitivity, because failure is extremely difficult to observe.

The easiest tool to use is CD-SEM (a scanning electron microscope), which can be used to detect various defects, but the disadvantage is that the observation area is limited, and it takes several months to scan a complete wafer. Another tool is E-beam, which has a larger scanning area, but the disadvantage is that the high-energy electron beam used is destructive to photoresist and the wafer-level scanning is still not efficient enough. Some companies use multi-electron beam scanning to try to solve the speed problem, but how to ensure the calibration of thousands of electron beams and how to ensure that the electron beams do not affect each other are problems they need to solve.

"Optical defect inspection is the ultimate solution that everyone wants to use. Its advantage is wafer-level scanning, which is exactly what the industry needs. Its detection sensitivity reaches 0.01/cm2." Peter De Bisschop said. Through the research and optimization of detection light and software, the field of optical inspection has made great progress in maximizing the signal-to-noise ratio.

Each method has its advantages and disadvantages

Disadvantages of optical inspection

It is worth noting that the benefits of optical inspection are based on the reliability of the technology, specifically, optical inspection has a sufficiently good signal-to-noise ratio for various defects. Admittedly, this is still an unresolved issue. Compared with CD-SEM, which can clearly display the exposure pattern, optical inspection does not show the details of the wafer. The principle of optical inspection is to compare the change of scattered light at the point to be inspected with a reference point. With enough light, extremely subtle changes in light intensity can be distinguished, but the human eye cannot see such defects.

In addition, optical defect detection can detect very small defects but it also comes at a price. Optical technology has been successfully applied to some relatively large defects such as particle defect detection, "but now, the defects have become so small that we can't help but ask ourselves, do optical methods have high enough sensitivity to detect these random defects, such as line bridging or hole loss? This is still an open question. Of course, for larger defect detection, optical technology is undoubtedly the only choice." Peter De Bisschop said.

So, we still lack a method that can do everything, and each technology has its own advantages and disadvantages. For example, for the detection of bridges, optical methods show different - but complementary - scopes than CD-SEM. CD-SEM is a good choice when measuring high-density defects. Extrapolating the data measured by CD-SEM by several orders of magnitude can get a very reasonable prediction trend (as shown below). At the same time, optical detection methods also have very good sensitivity for the detection of fine-sized bridge defects.

The rise of machine learning

Machine learning can make existing equipment more efficient. CD-SEM is much slower than SEM-Review because the former performs a detailed scan of each pixel, while the latter only performs a rough scan. "Of course, the faster the scan speed, the lower the resolution and sensitivity. However, we are trying to use machine learning, such as fast face recognition technology, to improve the high-quality imaging of defect detection. If it works, we can greatly speed up the scanning speed of the electron beam, and wafer-level scanning will not require 1,000 electron beams, but 100 beams will be enough," said Philippe Leray.

Another use of machine learning is in the control of the manufacturing process. In the manufacturing process of integrated circuits, a wafer will pass through a large number of devices, and each step is controlled by precise parameters and in-situ detection. A large amount of data will be generated in this process. For example, to detect the depth of plasma etching, we need to observe the spectrum of plasma, and the information contained in the image and spectrum is far more than just "defects" or depth. Philippe Leray said: "Our idea is to collect all the data throughout the integrated circuit manufacturing and measurement process to "train" the equipment to find patterns. The equipment understands defects by calculating and inferring critical dimensions (CD) or discovering bad etching through a large amount of data. Even if these data are so subtle and complex that they cannot be recognized by humans."

Cognition of a random world

In fact, these measurements have revealed the relationship between the probability of random failure and the exposure size: as the size decreases, the probability of failure increases almost exponentially. We call this relationship the "stochastic cliff". For dense structures, there are two types of failures: as the line distance and the size of the contact hole decrease, the two defects of line bridging or contact hole loss will increase sharply; and as the line width or the distance of the contact hole decreases, the two defects of line breakage or contact hole overlap will increase sharply. For sparser structures, both failure mechanisms exist, but only line breakage or contact hole loss or actual defects. The stochastic cliff is not the only problem. At this year's SPIE Advanced Lithography Conference, IMEC showed us their findings for the first time: the number of (bridging) defects will never decrease to zero, but reach a minimum constant, which we call a bottleneck. This is a very important discovery, revealing another mechanism for defect formation.

Although the mechanism of this bottleneck is not yet known, its consequences are very serious. The size that can be manufactured must be far away from the random cliff, and the defect-free window between the two cliffs for dense structures will be greatly reduced (see Figure a below). This is a problem that the industry needs to solve. The discovery of the bottleneck phenomenon means that "even in the defect-free window, it does not mean that there are no defects." Peter De Bisschop explained.

(a) There is a possible defect-free window between the two random cliffs

(b) For a given L/S (line/space) the number of bridging defects will not decrease to zero

Taking on random challenges

Once we know the random failures, we can develop targeted strategies to reduce the failure density. Currently, there are two aspects to achieve this goal: process parameter adjustment and failure mechanism research.

The exact location of the random cliff depends on the material used and a number of process parameters. You can tweak the process parameters but you won’t completely eliminate defects. Also, this is a delicate exercise. In real applications the structure and size of the pattern are different and all possible combinations of random cliffs may not result in a defect-free window.

This is why the industry is increasingly favoring the use of high-dose photoresists. The change in photoresist can improve one type of random cliff (microbridge defects), but surprisingly, it seems to have little effect on another type of random cliff (line breaks), and the same is true for bottleneck phenomena.

Size (a) and exposure dose

(b) Impact on random cliffs

Not only the exposure dose, but also the photoresist material is an important factor. IMEC has made some new progress in reducing random failures and line roughness by applying sequential penetration analysis (SIS) - an existing technology commonly used in directed self-assembly (DSA) - to EUV lithography technology, doping inorganic elements in the photoresist to make it harder and stronger, thereby improving the quality of the pattern.

“With so many parameters to tune, there should be an ‘optimal setting’ of parameters. But more likely, no single setting will solve the problem completely,” comments Peter De Bisschop. “Basically, we want to get to these optimal process parameters in a reasonable time. But many machines have hundreds of possible combinations of parameter settings, which is difficult to do manually. This is obviously another area where machine learning can help,” says Philippe Leray.

Study of failure

Understanding the failure mechanism can better deal with defects and understand the specific impact of process parameters on the probability of failure. EUV wavelength is very short, and high-energy photons bombard the photoresist, causing chemical reactions. The study of these chemical reactions can help develop photoresists and underlying absorption layers.

IMEC and KM Labs have recently started collaborating to study the fundamental physics of EUV lithography, making it possible to study the chemical reactions between EUV photons and photoresists at the attosecond to picosecond level. Currently, no other laboratory has this capability.

Study of EUV photons and photoresist chemistry is crucial to reduce random failures

Another way to uncover the mystery of EUV lithography is to detect and quantify which molecules are released during the lithography reaction. After absorbing photons, the photoresist undergoes a chemical reaction, the photoresist molecules decompose and form new chemical bonds, and another part of the material is unstable and escapes. The detector above the photoresist can detect these escaped molecules and analyze their composition by their mass. These chemical products did not exist before exposure, so their generation can reveal the lithography chemical reaction process. In addition, by detecting the reaction products, we can understand the impact of exposure dose or photoresist material on the lithography chemical reaction. In this way, we can link the pros and cons of lithography optical reactions to random failure types or probabilities.

"Of course, none of these strategies can fully reveal the face of the random world. But each method can give us a better understanding of the random world, and ultimately we hope that one day we will be able to fully understand the mechanism of the random world," Peter De Bisschop concluded.

**To read the original text, please click on the lower left corner.

*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.

Today is the 2057th issue of content shared by "Semiconductor Industry Observer" for you, welcome to follow.

Latest articles about

■SiC giant, rebirth: how to predict the future?

■Apple chips may hit Qualcomm hard

■Chip cost per car: soaring to $1,000

■TSMC 2nm, important information

■Huang Renxun's latest views

■The risks of this type of chips that are promising have increased significantly!

■NPU, how to see it?

■Storage giants are abandoning DDR 4

■Intel, why?

■Nvidia will definitely be disrupted