C6455 CSL_EMIF Detailed Explanation

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C6455 CSL_EMIF Detailed Explanation [Copy link]

ABSTRACT

When developing C6455 applications, you must use the CSL (Chip Support Library) provided by TI. The API provided by CSL has packaged the underlying implementation details for me, and we only need to call these APIs directly. However, in order to better use these APIs, it is necessary to carefully analyze how these API functions are implemented.

Add CSL header files and library files in CCS

CCS (Code Composer Studio) is a comprehensive development tool developed by TI for its DSP, MSP and other chips. The CCS5.x version is developed based on Eclipse, but I am not sure about the development platform of CCS4.x and its earlier versions.

I am using CCS5.2. In CCS5.x, the CSL library is not included by default in the CCS. You can download the latest CSL library at 查看详情 . The downloaded CSL library is as follows:

It contains the source code of this library implementation, the library files and header files we need, and an API Reference in PDF format.

From the above figure we can see that this version of CSL has made INTC (interrupt management) into a separate module , and other peripherals are placed in another module.

When using it, we must add the path where the header file and library file are located and the name of the library file to the project so that the compiler can find them when compiling and linking, otherwise it will prompt an error that it cannot be found.

EMIF

C6455 EMIF module

EMIF is the abbreviation of External Memory Interface. I think it is a more powerful DSP.

Through the EMIF interface, DSP and FPGA can easily transmit large amounts of data.

The EMIFA of C6455 can access a variety of external memories, such as SRAM, ROM, FLASH, etc. Of course, it also includes FPGA. The focus of this article is to introduce how to use the EMIFA interface to establish a seamless connection with FPGA.

This is the interface diagram of the EMIFA module given in the official document. At first glance, it is very complicated.

There are many pins that are reused. It doesn't matter. Let's post another one and you will feel much more relaxed. This picture first classifies the interfaces of the EMIFA module. Then, I marked the pins that need to be used in communication with the FPGA with red boxes. Isn't it a lot less? The marked pins are summarized as follows:

AED[63:0] 64-bit data bus

AEA[19:0] 20-bit address bus (Optional)

ACE2 chip select signal (low active)

AECLKOUT clock signal

ASWE write enable (active low)

ASRE Read Enable (Low Active)

(Note: The application scenario is that DSP reads the image data in the internal RAM of FPGA. Other scenarios will be adjusted according to the situation.)

Due to the programmability of FPGA, everything is much simpler from the perspective of DSP, because the "memory" faced by DSP is extremely intelligent, and even address lines are not needed.

Next, let’s analyze the above signals one by one.

First, the chip select signal CE should be mentioned. Here we have to mention the address space of DSP. The following figure is

EMIFA mapping of DSP6455

It can be seen from the figure

EMIFA supports a total of 4 external memories. For example, CE2 can be assigned to FPGA, CE3 to

allocated to SRAM, CE4 to FLASH, and so on.

The addressing space size of each external memory is 8MB. 20 address lines is 2 to the 20th power.

That is 1MB. In addition, since the data bus is 64 bits, the corresponding addressing space is 8MB.

Since the timing logic inside the FPGA can generate addresses, we do not need to use address lines. In this way, the following things are simple. Just connect the CE2 pin to a general IO port of the FPGA. When reading the RAM data inside the FPGA, tell EDMA that the base address of the data to be read is

0xA0000000 and the length of the data to be read.

The second signal, ECLKOUT, is the clock signal. Because FPGA requires clock excitation to work, how to generate address logic without a clock signal? In addition, the clock frequency cannot be too high, and the capabilities of the FPGA chip must be considered. OK, because there is a synchronous clock, the working mode of the EMIFA module

This determines the synchronous working mode.

The third signal includes two, namely ASRE and ASWE. More familiar names are RE and WE.

And write enable. I won't go into details about this.

The fourth signal, data bus & address bus, will not be described in detail.