A complete interpretation of TSMC’s technology roadmap: 5nm will arrive next year!
TSMC is undoubtedly the absolute king in the field of wafer foundry.
The list of the world's top 10 wafer foundries in Q2 2019 released by TrendForce shows that TSMC topped the list with a market share of 49.2% in Q2, far ahead of Samsung, which ranked second (with a market share of 18%). All this is due to their huge investment and deep accumulation over the past years.
Ranking of the world's top ten wafer foundries in the second quarter of 2019
At the TSMC 2019 China Technology Forum held in Shanghai yesterday, they demonstrated the company's strength in wafer foundry, and also disclosed the company's future development direction and a series of technical details such as some new process nodes, packaging, RF and eNVM.
Process route: 7nm dominates the market, 5nm is on the way
Driven by the demands of mobile, HPC, AI and 5G, 7nm process has become a hot commodity in the market. And so far, this is all TSMC's business.
The company's president, Wei Zhejia, said at yesterday's technical forum that TSMC is the world's first foundry to mass-produce 7nm technology. All chips manufactured using 7nm technology on the market are now produced by TSMC. Since mass production in 2018, the company has made important progress in 7nm.
According to reports, TSMC has obtained 60 NTOs (New Tape Out) for 7nm so far, and this number will exceed 100 in 2019. This has led to a surge in the company's 7nm production capacity. According to data, in 2018, TSMC's 7nm production capacity doubled compared to 2017, and the production capacity in 2019 will increase by 1.5 times compared to last year. It is revealed that TSMC's 7nm production capacity this year will be equivalent to 1 million 12-inch wafers, and the proportion of the company's revenue occupied by this process is also increasing.
TSMC's revenue distribution in Q1 2019 (by different nodes)
As shown in the figure above, from the financial report for Q1 2019, we can see that TSMC's 7nm process revenue accounted for as high as 22%, which is the largest contribution among TSMC's existing nodes. This proportion was not worth mentioning in the early part of last year. If we look at TSMC's financial report, we will find that they are now accustomed to digging out the first pot of gold for wafer foundry with advanced technology, which is also an obvious feature they have shown in recent years. Of course, this requires huge investment to achieve results.
After the 7nm process, TSMC launched the 7nm+ process. As TSMC's first node using EUV lithography technology, the logic density of TSMC's 7nm+ is 1.2 times that of the previous generation process (7nm), and its yield performance is comparable to that of 7nm. According to their plan, this process will be put into mass production in the second half of 2019.
After the 7nm and 7nm+ processes, TSMC launched the 6nm process. According to TSMC, this process will play an important role for quite a long time in the future.
From their introduction, we learned that thanks to their understanding of 7nm and EUV applied in 7nm+, they have grandly launched this process that can obtain smaller dies, increase logic density by 18%, and reduce process complexity and improve yield. It is understood that this process can support existing 7nm customers to transfer their IP and designs directly to the 6nm process. Developers do not need to make any changes and can directly produce using the design flow and EDA used in 7nm. This process will become the successor of 7nm+ and 7nm in the future, and it plays an important role in TSMC's 7nm plan. This process will also be trial-produced in Q1 2020.
After 6nm, TSMC also mentioned the 5nm process optimized for mobile and HPC applications at the technical forum. It was revealed that through innovative design, TSMC has improved the logic density, SRAM size and analog density of this generation of process by a level. This process also underwent risk trial production in March this year. The company estimates that it will be mass-produced in February next year. According to TSMC, this will be the first node using High Mobility Channel FinFET, and they will also become the world's first Foundry to enter 5nm.
After 5nm, TSMC has also planned a performance-enhanced version of the 5nm+ process. It is reported that this process will have a 7% speed increase and 15% power reduction compared to 5nm. It will share the same design rules as 5nm. From TSMC's introduction, we learned that they expect this process to be ready in 2020.
When talking about the process planning after 5nm+, TSMC talked about their views on advanced transistor structures such as FinFET and nanowires, High Mobility Channel, Ge and 2D materials. They also mentioned innovative low-k materials, which they believe will be the key support for the future evolution of semiconductor processes.
Advanced packaging: Layout from COWOS to WOW
After the process node entered 28nm, due to the limitations of the characteristics of the silicon material itself, it is basically impossible for wafer fabs and chip factories to continue to improve chip performance at the previous pace by miniaturizing transistors. For this reason, major manufacturers are now beginning to explore ways to improve performance starting from packaging, and TSMC is one of the pioneers among them.
First of all, TSMC's bumping service, which has penetrated into many customers' internal departments, is a basic part of TSMC's packaging business. According to reports, more than 90% of 7nm customers have chosen TSMC's bumping service.
The second is the Cowos business. Eight years ago, at TSMC's third quarter 2011 earnings conference, TSMC founder Morris Chang dropped a bombshell without warning: TSMC was going to enter the packaging field. The first advanced packaging product they launched was CoWoS (Chip on Wafer on Substrate). This means putting logic chips and DRAM on a silicon interposer and then packaging them on a substrate.
According to reports, since its launch, TSMC's COWOS packaging technology has been selected by more than 50 customers, and the company has also achieved the highest yield rate in the industry with this packaging technology. In their view, COWOS will become more and more important in the future, and market demand will gradually increase. TSMC will also optimize from all angles to simplify customers' COWOS design process and speed up product launch.
This packaging technology can also provide various supports for innovation.
In addition to bumping and COWOS, InFO (Integrated Fan-Out) is another killer weapon in TSMC's packaging arsenal. The so-called InFO is integrated fan-out technology. This is a non-perforation technology that is specially developed for cost-sensitive applications such as mobile and consumer products.
According to reports, this technology is divided into three categories: one is InFO_oS (Integrated Fan-Out on substrate), another is InFO_mS (Integrated Fan-Out memory on substrate), and the other is InFO_POP.
In addition, TSMC has also launched the alternative InFO process SoW (System on Wafer).
TSMC said that these two packaging technologies will play an important role in the company's advanced packaging layout, and will also be able to provide full-range support for chips such as AI, servers, networks, AI reasoning and mobile.
According to TSMC's classification, the above types belong to their back-end 3D packaging. In order to further promote the improvement of chip performance, TSMC has also launched the front-end 3D packaging process SOIC (system-on-integrated-chips) and the new multi-wafer stacking (WoW, Wafer-on-Wafer).
TSMC further stated that the result of back-end 3D packaging is that a chip that can be used directly is obtained, while using front-end packaging only obtains a heterogeneous chip, which still requires us to package it to obtain a usable chip.
SoIC is an innovative multi-chip stacking technology that can perform wafer-level bonding technology for processes below 10 nanometers. This technology has no protruding bonding structure, so it has better operating performance.
The revolutionary process technology Wafer-on-Wafer (WoW) stacks two layers of dies vertically in a mirrored manner, just like the multi-layer stacking of 3D NAND flash memory. It is expected to be used in the production of graphics card GPUs to create GPUs with larger transistors. It is reported that the WoW technology connects the upper and lower dies through 10μm silicon vias, so that more dies can be stacked vertically, which also means that the delay communication between dies is greatly reduced, and more cores can be introduced.
More than just logic chips: exploring greater growth space
TSMC is best known for its performance in logic chips. In fact, in addition to logic chips, they have also made great progress in many fields.
First, let's look at the RF aspect. On the one hand, TSMC is advancing the process to 16nm FinFET for markets such as WiFi and millimeter wave. The company will make the entire node have better performance through process transformation. According to their estimates, spice/SDK will be launched in Q1 2020. From the figure below, we can see that TSMC will even launch a 7nm RF process, and the related spice and sdk will be ready in the second half of 2020. TSMC is also investing in RF-SOI to obtain more comprehensive RF product foundry services.
TSMC also has an extensive layout in the analog field.
CIS foundry is also an area where TSMC performs well;
Highly sensitive microphones are also a focus for TSMC.
There are also processes prepared for high-end OLEDs.
The process prepared for PMIC also performed well.
It is worth mentioning that TSMC is also investing in eNVM and exploring the use of eFLASH as a replacement for MCU and other applications. According to reports, their 40nm RRAM has been put into risk trial production in the first half of 2018, and 28nm/22nm RRAM will also be put into risk trial production in the second half of 2019; they also have 22nm MRAM, which has a write speed three times faster than eflash, and this process has also been put into risk trial production in the second half of 2018.
As mentioned earlier, TSMC’s huge investment has contributed greatly to the above success.
According to reports, TSMC's annual R&D investment has reached 10 billion US dollars in recent years. Driven by these continuous investments, in addition to technological progress, the company's production line capacity has also reached 12 million 12-inch wafers and 11 million eight-inch wafers per month.
These accumulated investments, together with the OIP (open innovation platform) created by TSMC in collaboration with EDA and IP companies, have become the foundation for TSMC to conquer the future market.
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
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