[Revelation] This is how semiconductor manufacturers conduct factory testing of chips

Latest update time：2021-09-03 08:04

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Large companies produce tens of thousands of chips every day , and the pressure of testing is very high. When the chips are produced by the wafer factory , they will enter the wafer test stage. This stage of testing may be carried out in the wafer factory or sent to a nearby testing manufacturer for execution.

Production engineers use automatic test equipment (ATE) Run the program provided by the chip designer to simply and roughly divide the chip into good / The two bad parts , The bad ones will be discarded directly. , If there are too many bad films at this stage , It is generally believed that the wafer fab itself has a low yield rate. If the yield rate drops below a certain value, , Fabs need to lose money.

WT The test results are often represented by a graph like this :

After passing WaferTest , the wafer will be cut, and the cut chips will be classified according to the previous results. Only good chips will be sent to the packaging factory for packaging. The packaging location is usually near the wafer factory , because unpackaged chips cannot be transported over long distances. The type of packaging depends on the needs of the customer. Some require ball BGA, and some require pins . In short, this step is very simple and there are fewer failures. Since the success rate of packaging is much higher than the production yield rate of the chip , there will be no testing after packaging.

After packaging , The chips will be sent to the testing factories of major companies. , Also called a production plant. And conduct Final Test , the production plant actually has more than a dozen processes , FinalTest Just the first step. exist Final Test back , It also requires steps such as sorting, engraving, inspection, packaging, etc. before it can be shipped to the market.

Final Test The focus of the factory , Requires a lot of machinery and automation equipment . Its purpose is to strictly classify chips. by Intel Take the processor as an example , exist Final Test These phenomena may occur in :

1. Although passed Wafer Test, But the chip is still bad.

2. Package damage

3. Partial chip damage . for example CPU have 2 Core damaged , or GPU damage , Or the display interface is damaged, etc.

4. The chip is good , No malfunction

At this time , Engineers need to work with the marketing department to decide , How to classify these chips? For example , GPU broken , Can be used as a graphics core " Celeron " series processors. If CPU broken 2 individual , Can be " core i3" Series processors. The chip is working properly , But the working frequency is not high , Can be " core i5" Series processors. No problem at all , Can be " core i7" processor. ( The above is just a simplified description " The results of chip testing affect the final label of the product " this process , It's not that Intel The chip mass production line is as described above. Intel At the same time, we maintain multiple product lines. i3 and i7 The chips are not produced on the same assembly line. )

That here Final Test What to do ?

Take the processor as an example , Final Test Can be divided into two steps :

1 , Automatic test equipment (ATE)

2 , System level testing (SLT)

ATE The test usually takes a few seconds , and SLT It takes several hours. ATE The existence of greatly reduces the chip testing time.

ATE Responsible for many projects , And there is a strong logical connection. Tests must be performed in order , Test results for the front , The following tests may be skipped. . The contents of these items are company confidential , I will only list a few, such as power supply detection , Pins DC Detection , Test Logic ( Generally JTAG) Detection , burn-in, Physical Connections PHY Detection , IP Internal testing ( include Scan, BIST, Function wait ), IP of IO Detection ( for example DDR, SATA, PLL, PCIE, Display wait ), Accessibility testing ( For example, thermodynamic properties , Fuse, etc. ) .

These tests will give Pass/Fail, According to these Pass/Fail To analyze the physical properties of the chip , It's the job of a test engineer.

SLT Logically it is simpler , Install the chip on the motherboard , Configure memory, peripherals, start an operating system, and then test it with software , Record the results and compare them. Also test BIOS Related items, etc.

Test plant layout

All of this work , All of them need to be designed by chip design engineers before tape-out. The testing work is done by dedicated circuits inside the chip. , This part of the circuit is built by DFT Engineers do it , After tape-out , DFT Engineers also need to generate matching input vectors , Generally, tens of thousands of vectors will be generated. Whether these vectors can detect the function of the chip normally , Product development engineers are needed to ensure this. In addition, test engineers are also needed. , product engineer , Together with the assistant, we can ensure that the production of tens of thousands of chips can be completed every day without any problems due to the test logic. Bugs And delay.

Considering that each test version iteration is hundreds of thousands of lines of code , Ensure that the code is error-free. Hundreds of test engineers need to work together , This is not an assembly line technician. , Therefore, testing is a time-consuming and laborious task. , The testing costs of chips for many large companies are already close to their R&D costs.