SAM G55G / SAM G55J
Atmel | SMART ARM-based Flash MCU
SUMMARY DATASHEET
Description
The Atmel
®
| SMART SAM G55 is a series of Flash microcontrollers based on the
high-performance 32-bit ARM
®
Cortex
®
-M4 RISC processor with FPU (Floating
Point Unit). It operates at a maximum speed of 120 MHz and features 512 Kbytes
of Flash and up to 176 Kbytes of SRAM. The peripheral set includes eight flexible
communication units comprising USARTs, SPIs and I
2
C-bus interfaces (TWIs),
two three-channel general-purpose 16-bit timers, two I
2
S controllers, one-channel
pulse density modulation, one 8-channel 12-bit ADC, one real-time timer (RTT)
and one real-time clock (RTC), both located in the ultra low-power backup area.
The Atmel | SMART SAM G55 devices have three software-selectable low-power
modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while
all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on
events, including partial asynchronous wakeup (SleepWalking™). In Backup
mode, RTT, RTC and wakeup logic are running.
For power consumption optimization, the flexible clock system offers the capability
of having different clock frequencies for some peripherals. Moreover, the
processor and bus clock frequency can be modified without affecting the
peripheral processing.
The real-time event management allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM G55 devices are general-purpose low-power microcontrollers that offer
high performance, processing power and small package options combined with a
rich and flexible peripheral set. With this unique combination of features, the SAM
G55 series is suitable for a wide range of applications including consumer,
industrial control and PC peripherals.
The device operates from 1.62V to 3.6V and is available in three packages:
49-pin WLCSP, 64-pin QFN and 64-pin LQFP.
Atmel-11289ES-ATARM-SAM-G55G-SAM-G55J-Summary-Datasheet_25-May-16
Features
Core
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ARM Cortex-M4 with up to 16 Kbytes SRAM on I/D bus providing 0 wait state execution at up to
120 MHz
(1)
Memory Protection Unit (MPU)
DSP Instructions
Floating Point Unit (FPU)
Thumb
®
-2 instruction set
1. 120 MHz with V
DDCOREXT120
or with V
DDCORE
trimmed by regulator.
Note:
Memories
̶
̶
̶
Up to 512 Kbytes embedded Flash
Up to 176 Kbytes embedded SRAM
8 Kbytes ROM with embedded boot loader, single-cycle access at full speed
̶
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̶
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̶
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Embedded voltage regulator for single-supply operation
Power-on reset (POR) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for
RTT or system clock
High-precision 8/16/24 MHz factory-trimmed internal RC oscillator. In-application trimming access for
frequency adjustment
Slow clock internal RC oscillator as permanent low-power mode device clock
PLL range from 48 MHz to 120 MHz for device clock
PLL range from 24 MHz to 48 MHz for USB device and USB OHCI
Up to 30 peripheral DMA (PDC) channels
256-bit General-Purpose Backup Registers (GPBR)
16 external interrupt lines
̶
8 flexible communication units supporting:
USART
SPI
Two-wire Interface (TWI) featuring TWI masters and high-speed TWI slaves
Crystal-less USB 2.0 Device and USB Host OHCI with On-chip Transceiver
2 Inter-IC Sound Controllers (I
2
S)
̶
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1 Pulse Density Modulation Interface (PDMIC) (supports up to two microphones)
2 three-channel 16-bit Timer/Counters (TC) with capture, waveform, compare and PWM modes
1 48-bit Real-Time Timer (RTT) with 16-bit prescaler and 32-bit counter
1 RTC with calendar and alarm features
1 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
̶
Up to 48 I/O lines with external interrupt capability (edge or level), debouncing, glitch filtering and on-
die series resistor termination. Individually programmable open-drain, pull-up and pull-down resistor
and synchronous output
Two PIO Controllers provide control of up to 48 I/O lines
System
Peripherals
̶
I/O
̶
2
SAMG55 [SUMMARY DATASHEET]
Atmel-11289ES-ATARM-SAM-G55G-SAM-G55J-Summary-Datasheet_25-May-16
Analog
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One 8-channel ADC, resolution up to 12 bits, sampling rate up to 500 ksps
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49-lead WLCSP
64-lead LQFP
64-lead QFN
̶
Industrial (-40°C to +85°C)
Package
Operating Temperature Range
SAMG55 [SUMMARY DATASHEET]
Atmel-11289ES-ATARM-SAM-G55G-SAM-G55J-Summary-Datasheet_25-May-16
3
1.
Configuration Summary
Table 1-1
summarizes the SAM G55 device configurations.
Table 1-1.
Configuration Summary
Feature
Flash
Cache (CMCC)
SRAM
Package
Number of PIOs
Event System
External Interrupt
12-bit ADC
SAM G55G19
512 Kbytes
up to 8 Kbytes
160 Kbytes
+ up to 16 Kbytes (Cache + I/D RAM)
WLCSP49
38
Yes
16
8 channels
Performance: 500 kSps
6 channels
(3 external channels)
2 / 1-channel 2-way
28
SAM G55J19
512 Kbytes
up to 8 Kbytes
160 Kbytes
+ up to 16 Kbytes (Cache + I/D RAM)
QFN64, LQFP64
48
Yes
16
8 channels
Performance: 500 kSps
6 channels
(3 external channels)
2 / 1-channel 2-way
30
16-bit Timer
I2SC/PDM
PDC Channels
USART
SPI
TWI
USB
CRCCU
RTT
RTC
7
8
Full Speed / OHCI
1
1 (backup area)
1 (backup area)
Full Speed / OHCI
1
1 (backup area)
1 (backup area)
4
SAMG55 [SUMMARY DATASHEET]
Atmel-11289ES-ATARM-SAM-G55G-SAM-G55J-Summary-Datasheet_25-May-16
2.
Block Diagram
Figure 2-1.
SAM G55 Block Diagram
O
TM
S
TC /SW
K/ D
SW IO
JT
CL
AG
K
SE
L
O
DI
VD
DO
VD
UT
TD
TST
PCK[2:0]
PLLA
VDDUSB
(64-pin package only)
PLLUSB
RC OSC
8/16/24 MHz
Power
Management
Controller
TD
I
Voltage
Regulator
JTAG and Serial Wire
In-Circuit Emulator
ERASE
Backup area
Supply
Controller
Tamper Detection
Cortex-M4 Processor
f
MAX
120 MHz
DSP
MPU
NVIC
24-bit SysTick
Counter
FPU
WKUP[15:0]
XIN32
XOUT32
XIN
XOUT
Power-on
Reset
Real-time
Clock
32K OSC
32K RC
256-bit
General-purpose
Backup Registers
I
D
SRAM
CMCC
2/4/8 KB Cache
Up to 16 Kbytes
S
Flash
Unique
Identifier
User
Signature
VDDIO
M
M
Flash
S
S
512 Kbytes
Real-time
Timer
NRST
VDDCORE
Watchdog
Timer
Reset
Controller
Supply
Monitor
4-layer AHB Bus Matrix
f
MAX
120 MHz
S
M
M
SRAM
160 Kbytes
M S
ROM
8 Kbytes
PIOA/PIOB
CRCCU
AHB/APB
Bridge
PDC
DMA
System Controller
USB OHCI
Transceiver
MUX
DP
DM
2668
bytes
FIFO
USB 2.0
Full-speed
PDMIC_DAT
PDMIC_CLK
PDC
PDMIC0
PDMIC1
PDC
I2SCK0...1
I2SWS0...1
I2SDI0...1
I2SDO0...1
I2SMCK0...1
PDC
2 x I2SC
FLEXCOM
SCK_SPCK0...7
TXD_MOSI_TWD0...7
RXD_MISO_TWCK0...7
RTS_NPCS1_0...7
CTS_NPCS0NSS_0...7
PDC
8x
USART, SPI, TWI
Timer Counter A
TC[0..2]
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
Timer Counter B
Event System
TC[3..5]
AD[7:0]
ADTRG
PDC
12-bit ADC
SAMG55 [SUMMARY DATASHEET]
Atmel-11289ES-ATARM-SAM-G55G-SAM-G55J-Summary-Datasheet_25-May-16
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