The next step for transistors!

Latest update time：2024-02-24

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Source : Content compiled from semiengineering by Semiconductor Industry Observation (ID: i c bank ), thank you.

Later versions of vertical transistors are emerging as possible successors to finFETs, combining lower leakage with significant area reduction.

The stacked nanosheet transistors introduced with N3 use multiple channel layers to maintain overall channel length and necessary drive current while continuing to reduce standard cell footprint. A follow-up technology, CFET, pushes the z-axis further up, stacking n-channel and p-channel transistors on top of each other instead of side by side.

In work presented at the IEEE Electronic Devices Conference in December, TSMC researchers estimated that CFETs can reduce overall size by a factor of 1.5 to 2 times while maintaining a constant gate size. These are significant domain advantages for any digital logic, but fabricating these new transistor structures will be a challenge.

Monolithic 3D integration is the simplest integration solution and the one most likely to be put into production first. In monolithic 3D integration, the entire structure is assembled on a single piece of silicon. This approach can also be used to fabricate in-memory computing designs, where memory devices are fabricated as part of the metallization layers of traditional CMOS circuits. While individual layers within a monolithic 3D design can incorporate new technologies (such as the integration of ReRAM devices), the overall CMOS process remains. All materials and processes used must be compatible with this standard.

Adding more nanosheets to complementary devices

The overall process of this approach is similar to the stacked nanosheet transistor process. It starts with eight or more alternating layers of silicon and silicon germanium (four pairs), whereas a stacked nanosheet NFET or PFET may have only four such layers (two pairs). However, in the CFET process, an intermediate dielectric layer is inserted into the middle of the stack.

This layer separates n-type and p-type transistors and is perhaps the most important difference from standard nanosheet transistor flow. Naoto Horiguchi of imec says that to minimize parasitic capacitance, the intervening dielectric layer should be as thin as possible. But if it's too thin, incorrect edge placement can cause isolation to fail, dropping the top device's contacts onto the bottom device.

In TSMC's process, the Si/SiGe superlattice includes a high-germanium SiGe layer as a placeholder for the intervening dielectric. After the source/drain etch, a highly selective etch removes this layer and oxidizes the silicon on either side of it to form an intervening dielectric.

After the intermediate dielectric is formed in the TSMC process, an internal spacer recess etch is performed to recess the SiGe layer relative to the silicon nanosheet, thereby defining the gate length and junction overlap.

Although TSMC emphasizes that it has yet to create fully metallized integrated CFET circuits, it does report that more than 90% of the transistors survived.

Depositing stacks of nanosheets is very simple. Etching it with the required precision does not. An etch profile that is less than vertical will change the relative channel lengths of the top and bottom devices, resulting in asymmetric switching characteristics.

Stacking wafers for greater flexibility

Another kind of sequential 3D integration is more flexible. While monolithic 3D integration uses a single device layer, sequential 3D integration bonds an additional layer on top of the first layer. However, sequential 3D integration is different from 3D wafer-level packaging and chip stacking. In WLP, component devices are completed, passivated, and tested. Component chips are fully functional as independent circuits. In sequential 3D integration, these two layers are part of a single integrated circuit.

Typically, although not always, the second layer is an unprocessed bare wafer without any devices at all. Ionut Radu, director of research and external partnerships at Soitec, said his company uses the SmartCut process to transfer submicron silicon layers. However, one of the advantages of sequential integration is that it opens the door to other possibilities. For example, the second layer could use a different silicon lattice orientation to facilitate stress engineering to increase carrier mobility. It could also use alternative channel materials such as gallium arsenide or two-dimensional semiconductors. The processing of the second wafer has no impact on the thermal budget of the first wafer until the transfer occurs.

After bonding, the process temperature of the second layer must typically be kept below 500°C. Tadeu Mota-Frutuoso, a process integration engineer at CEA-Leti, said the researchers were able to achieve this benchmark in a conventional CMOS process by using laser annealing of the source/source. Drainage activation steps.

Although sequential 3D integration can be used to implement CFET devices, the top layer can also contain independent circuits. Still, as with monolithic integration, the dielectric layer between the two circuit layers is a critical process step. Analysts at KAIST found that reducing the thickness of the interlayer dielectric can improve heat dissipation. It also helps to use the bottom gate to control the top device. The dielectric layer, on the other hand, is located at the interface between the original wafer and the transfer layer. Thickness control depends on the polishing steps used to prepare the transfer surface. Such precise control is extremely challenging for CMP.

Re-drive wafers without contamination

While a second circuit layer can be added at any point in the process flow, the insertion point limits not only the first and second layer devices, but the entire fab. Alignment to the first layer is relatively easy when the second layer does not yet contain devices. In contrast, Horiguchi said aligning one device wafer on top of another incurs an area penalty to accommodate potential overlay errors. The total device thickness also tends to be greater for sequential 3D structures.

Returning the first-layer wafer with contacts and other metallization to the FEOL tool to fabricate the second transistor layer poses a significant risk of cross-contamination. Even if the top surface is well packaged, Mota-Frutuoso explained in an interview, the sidewalls and bevels of the bottom layer will still expose the metal layer to the FEOL process. To solve this problem, CEA-Leti proposed a Bevel Contamination Wrap (BCW) approach that first cleans the wafer edge and then encapsulates it and the sidewalls with a protective oxide layer.

Control cooling

Heat dissipation is a significant challenge for both monolithic and sequential 3D devices. Generalizations are difficult because thermal characteristics depend on the specific integration scheme and even circuit design. TSMC senior manager Wei-Yen Woon and his colleagues evaluated aluminum nitride and diamond as possible heat-sink layers. Although both have been used in power devices, they are new to the CMOS process flow. They obtained high-quality columnar AlN films through a low-temperature sputtering process, although the columnar structure did hinder in-plane heat transfer. Although diamond has extremely high thermal conductivity, it can also require extremely high processing temperatures. The TSMC team has deposited films of acceptable quality at BEOL-compliant temperatures using pre-deposited diamond cores, but they have not yet attempted to integrate these films with working devices.

What's next?

In the short term, monolithic 3D integration offers a relatively simple path to CFET manufacturing based on existing nanosheet transistor process flows. Even proponents of sequential 3D integration want the holistic approach to be in production first. But in the long term, the ability to use completely different materials on the second device layer gives device designers more process optimization knobs.

Regardless of how it's implemented, the idea that active devices no longer need to confine themselves to a single planar layer has implications far beyond logic transistors. From in-memory computing modules to image sensors, 3D integration is an important tool for “beyond Moore” devices.

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https://semiengineering.com/building-cfets-with-monolithic-and-sequential-3d/

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