TSMC 2nm, made important progress

Speaking to partners at Europe's annual Open Innovation Platform Forum last week, TSMC said a large part of TSMC's show is dedicated to the company's next-generation foundry technology. TSMC's 2nm N2, N2P and N2X process technologies will introduce multiple innovations, including nanosheet gate-all-around (GAA) transistors, backside power delivery and super-high-performance metal-insulator-metal (SHPMIM) insulator-metal) capacitors for the next few years.

But TSMC warned that to take advantage of these innovations, chip designers will need to use new electronic design automation (EDA), simulation and verification tools and IP. While making such a big shift is never easy, TSMC has brought some good news to chip designers early on: Even if N2 is still several years away, many major EDA tools, verification tools, basic IP and even N2's analog IP are already available.

"For N2, we can work with them two years in advance because Nanosheet is different," Dan Kochpatcharin, director of design infrastructure management at TSMC, said at the OIP 2023 conference in Amsterdam. "The [EDA] tools have to be ready, so what OIP does The thing is to work with them early. We have a large engineering team working with EDA partners, IP partners, [and other] partners.”

Preparations for production of N2 chips, originally scheduled to begin sometime in the second half of 2025, began early. Nanosheet GAA transistors behave differently than familiar FinFETs, so EDA and other tool and IP manufacturers must build their products from scratch. This is where TSMC’s Open Innovation Platform (OIP) shows its strength, enabling TSMC’s partners to start developing their products early.

Currently, mainstream EDA tools such as Cadence and Synopsys , as well as many EDA tools such as Ansys and Siemens, have passed TSMC certification, and chip developers can already use these tools for chip design. Additionally, EDA software programs from Cadence and Synopsys are ready for analog design migration. In addition, Cadence's EDA tools already support N2P backside power supply networks.

With pre-built IP designs, things take longer. TSMC 's foundation libraries and IP, including standard cells, GPIO/ESD, PLL, SRAM and ROM, are ready for mobile and high-performance computing applications. At the same time, some PLLs exist in pre-silicon development kits, while other PLLs are silicon-proven. Finally, modules such as non-volatile memory, interface IP, and even chiplet IP are not yet available - becoming a bottleneck for some chip designs - but are being actively developed or planned by Alphawave, Cadence, Credo, eMemory, GUC, and others Developed, according to TSMC's slides, by Synopsys. Ultimately, the ecosystem of tools and libraries for designing 2nm chips is consolidating, but it's not all there yet.

"[Developing IP with nanosheet transistors] is not difficult, but it does require more cycle time, and the cycle time is a bit long," Kochpatcharin said. "Some of these IP vendors also need training, [because] they're just different. Going from planar [transistors] to FinFETs, it's not hard, you just have to know how to make FinFETs. [It's] the same thing, you just have to know How to do [this]. So, it does take some time to get trained, but [when you get trained], it's easy, so that's why we started early."

While many of the chip's major building blocks already support N2, many companies still have a lot of work to do before TSMC's 2nm-scale process technology can be put into mass production. Large companies that tend to design (or co-design) their own IP and development tools are already developing 2 nm chips and should have products ready when volume production begins in February 2025. Other players can also fire up their design engines, as TSMC and its partners are well underway with 2nm preparations.

This year, TSMC will celebrate the 15th anniversary of its Open Innovation Platform, a multi-faceted initiative that brings together foundry suppliers, partners and customers to help TSMC’s customers better build innovations efficiently and in a timely manner chip. The OIP program has grown over the years and now involves dozens of companies and more than 70,000 IP solutions for a variety of applications. It continues to grow and will be more important than ever when next-generation technologies (such as 2 nm) and advanced packaging methods become mainstream in the coming years.

台积电设计基础设施管理主管 Dan Kochpatcharin 在荷兰阿姆斯特丹举行的 OIP 2023 会议上表示：“这不是一个营销计划，它实际上是一个为行业提供支持的工程计划。” “我们拥有一支庞大的工程团队来与 EDA 合作伙伴、IP 合作伙伴和设计合作伙伴合作。”

加快上市时间是台积电 OIP 计划的基石之一。在2008年OIP计划出现之前，台积电将在大约18个月的时间内开发出工艺技术和工艺开发套件（PDK），然后将PDK和设计规则移交给其电子设计自动化（EDA）软件和IP开发商中的合作伙伴。后者将再花费 12 个月创建 EDA 工具并构建 IP 模块，然后向实际芯片设计人员提供程序和 IP 解决方案。然后，芯片开发商还需要 12 个月的时间来构建实际的芯片。

借助 OIP，台积电的 EDA 工具和 IP 设计合作伙伴可以在台积电开始开发其新生产节点几个月后开始开发其产品。而且，代工厂声称，当台积电最终确定其工艺技术时，EDA 工具和 IP 已经为芯片设计人员准备好了。台积电表示，这将产品上市时间缩短了约 15 个月。与此同时，随着新节点的开发时间和芯片的开发时间越来越长，台积电与 EDA 和 IP 提供商之间早期合作的价值正在增加。

例如，台积电两年来一直在与合作伙伴进行 N2（2 纳米级）EDA 和 IP 准备工作，台积电的目标是在 2025 年下半年为芯片设计人员准备好工具和通用 IP。

热心的读者可能会想知道，为什么即使该计划取得了成功，OIP 在 15 年内只增长到 39 个 IP 成员。Dan Kochpatcharin 表示，事实证明，台积电对加入该计划的公司极为挑剔。台积电需要 OIP 计划的成员真正为其做出贡献，并使共同努力大于所有部分的总和。由于台积电客户使用 OIP 计划参与者提供的 IP、软件和服务，因此后者必须在其领域非常出色才能成为 OIP 的一部分。

事实上，台积电甚至有其 TSMC9000 计划（名称模仿 ISO 9000 质量政策），为 IP 设计设定质量要求。IP 合作者接受 TSMC9000 评估，结果可在 TSMC-Online 上获取，为客户提供有关 IP 可靠性和风险的指导。

“我们对 IP 进行了大量的资格认证，在 test shuttles进行流片之前，他们有 TSMC 9000 检查表，[...]客户可以在 TSMC-Online 上看到[所有]结果，”Kochpatcharin 解释道。“所以，他们可以看到，这个 IP 得到了硅片的引入，因此，他们对该 IP 更有信心。[他们还看到]有多少客户采用了 [这个 IP]、有多少流片以及有多少产品。对于缺乏更好的术语，即知识产权消费者报告。”

联盟成员在台积电的首要目录中列出了他们的 IP，其中包含来自 39 个贡献者的数千个 IP 选项。客户可以使用台积电在线设计门户上的“IP中心”搜索IP。目录中的每个 IP 均由其原始合作伙伴开发、销售和支持。同时，芯片开发人员甚至可以查看一个IP或另一个IP的受欢迎程度，这可以让芯片开发人员对他们的选择更有信心。如今，信心非常重要，而且对于 3 纳米、2 纳米以及未来的节点来说，随着流片变得更加昂贵，信心将变得更加重要。

但加快上市时间和确保质量并不是 OIP 计划的唯一目的。它旨在简化芯片的开发、生产、测试和封装。台积电的 OIP 涉及多种成员，并分为六个计划或联盟，每个计划或联盟负责不同的工作：

一、IP 联盟专注于提供经过硅验证、生产验证和代工厂特定的知识产权 (IP)，供台积电客户选择。

二、EDA 联盟包括提供符合台积电技术要求并支持代工厂生产节点的电子设计自动化 (EDA) 软件的公司。

三、设计中心联盟由合约芯片设计师以及提供系统级设计解决方案支持的公司组成。

四、云联盟结合了 EDA 工具制造商和云服务提供商，使台积电的客户能够在云中开发和模拟他们的芯片，以减少内部计算需求。

五、3D Fabric Alliance 联合了所有负责先进封装和多芯片处理器开发的公司，主要包括上述所有公司以及存储器制造商（包括美光、三星和 SK Hynix）、基板、OSAT、和测试设备制造商。

六、价值链联盟类似于设计中心联盟，但旨在提供更广泛的合同芯片设计服务和 IP 产品，以满足从初创公司、OEM 到 ASIC 设计人员等广泛客户的需求。

3D Fabric Alliance计划于去年年底推出，因此可以被认为是OIP的最新成员。与此同时，3DFabric 联盟希望通过新成员快速扩张，这是有原因的。

工艺技术变得越来越复杂，这一点不会改变。随着 Ansys、Cadence、Siemens EDA 和 Synopsys 等 EDA 制造商将人工智能功能融入到他们的工具中，芯片设计工作流程可能会变得更加容易。但由于高数值孔径 EUV 光刻扫描仪将掩模版尺寸从 858 mm2减半至 429 mm2，看来大多数人工智能和高性能计算 (HPC) 处理器将在未来几年采用多块设计，这将推动对有助于创建多块解决方案、先进封装、HBM 型存储器和全新测试方法的软件的需求。这将再次增加全行业合作的重要性以及台积电OIP的重要性。

“[我们自 2016 年以来一直提供 InFO_PoP] 和 InFO_oS 3D IC，[3D IC 已经]投入生产多年，[但]当时它仍然是一个利基[市场]，”Kochpatcharin 说。“客户必须知道他们在做什么 [...]，而 [当时] 只有少数人可以制作 3D IC。[2021 年]，我们推出了 3DFabric 活动，我们希望使其对所有人通用，因为有了人工智能和[来自多家公司]的 HPC，[这些] 不再是小众事物。因此，每个人都必须能够使用 3D IC。[例如]，汽车是 3D IC 的一个精彩[应用]，有一个[巨大的市场]。] 市场在那里。”

与此同时，为了实现芯片之间和小芯片之间的下一代连接，台积电预计将需要硅光子学，因此该公司正在其 OIP 计划中积极朝这个方向努力。

“如果你进入 N2，下一个出现的就是硅光子学，”Kochpatcharin 说。“我们在这里启动了一个流程，需要 [设计服务合作伙伴] 才能为客户提供支持。”

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