Storage vendors are racing to add more layers to 3D NAND, a competitive market driven by an explosion of data and demand for higher-capacity solid-state drives and faster access times.

Micron is already completing orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin mass production of 238-layer 512Gb triple-layer cell (TLC) 4D NAND in the first half of next year. Perhaps more importantly, chipmakers have privately said they will use industry learning to stack NAND for the 3D-ICs they are currently developing.

"Moore's Law for processors has been lagging behind over the past few years, but it's still alive and well for NAND flash memory," said Ben Whitehead, technical product manager for EDA at Siemens. "That's a good thing because modern computing and networking require fast speeds. There’s an insatiable demand for storage.”

SK Hynix launched the 4D nomenclature of 96-layer NAND in 2018. Despite the name, the company doesn't create its products in four dimensions or imitate the tesseract cube. But the term isn't exactly a marketing gimmick either. It is the trade name for a variant of 3D architecture.

"With DRAM, it takes about 10 or 15 years of research and development to come to fruition, but with 3D NAND, the pace of development is very fast. When you think about the usual development speed, you will be surprised," said Xi-Wei Lin, director of R&D at Synopsys. "In addition to the technology itself, it is also a killer application. Apple was the first to put in flash memory to store data. Today, when we buy an iPhone, we still look at how much memory it has, and it is all flash memory. From there, big data, artificial intelligence Intelligence and analytics require high-performance computing. Flash memory is filling this critical latency gap between hard drives and RAM memory because of the power consumption, form factor, and density costs you are seeing in applications, especially in data centers, analytics and. gaming field.”

Looking back at 2D NAND, it has a planar architecture with the floating gate (FG) and peripheral circuitry adjacent to each other. In 2007, as 2D NAND reached its scale limit, Toshiba proposed a 3D NAND structure.

Samsung was the first to introduce what it called "V-NAND" in 2013.

The 3D design introduces alternating layers of polysilicon and silicon dioxide and swaps the floating gate for charge trap flash (CTF). The differences are both technical and economic. FG stores memory in a conductive layer, while CTF "traps" charge in a dielectric layer. Due to reduced manufacturing costs, CTF designs quickly became the preferred choice, but certainly not the only one.

IBM researcher Roman Pletka noted: "While all manufacturers are moving to charge trap cell architectures, I expect traditional floating-gate cells to still play a significant role in the future, especially for capacity or retention-sensitive use cases."

Still, Hynix said that despite innovating skyscraper-like stacking, the first generation of 3D NAND designs kept peripheral circuitry aside.

Eventually, 3D NAND vendors moved peripheral circuitry under the CTF. In SK Hynix terms, it's now the Periphery Under Cell (PUC) layer. On one hand, saying "4D NAND" is shorter and cooler than CTF/PUC NAND. On the other hand, this is ultimately another variant of 3D NAND with smaller cell area per unit. Similar designs for smaller sizes are available under different trade names, such as Micron's CMOS under Array (CuA).

Figure 1: SK Hynix’s explanation of 4D NAND.

Source: SK hynix Global Newsroom.

Figure 2: Peripheral circuitry is the bottom layer of 4D NAND.

Source: SK hynix Global Newsroom.

Micron itself announced the launch of 232-layer NAND in late July 2022, which is in production. Micron said its 232-layer NAND is a watershed moment in storage innovation, demonstrating for the first time the ability to scale 3D NAND beyond 200 layers in production, according to the company's press release.

"The main thing adding these tiers does is increase capacity because everyone is looking for more SSD capacity," said Marc Greenberg, group director of product marketing at Cadence. "So adding more layers basically means you can store more gigabytes in a single package, on a single type of multi-layer 3D NAND component. It's a capability play, adding all these layers and the technology behind it.”

Micron also claims the industry's fastest NAND I/O speeds—2.4 Gbps—with a 100% improvement in write bandwidth and more than 75% improvement in read bandwidth per chip compared to the previous generation. In addition, the 232-layer NAND contains six planes of TLC-produced NAND, which Micron says are the most planes per die of any TLC flash memory, and enables independent read capabilities on each plane.

According to industry analysts, this may be the most impressive part of the announcement. Since there are six planes, this chip can behave as if it were six different chips.

Figure 3: Micron’s 232-layer NAND.

Source: Micron

China's Yangtze Memory Technology Co., Ltd. (YMTC) also announced the launch of a 232-layer 3D NAND module. It's unclear when it will enter mass production.

At last year's IEEE IEDM Forum, Samsung's Kinam Kim gave a keynote speech in which he predicted there would be 1,000-layer flash memory by 2030. This may sound dizzying, but it's not exactly science fiction. "Compared to the historical trend line for NAND flash memory, this has slowed down," said Maarten Rosmeulen, program director for storage memory at Imec. "If you look at other companies, like Micron or Western Digital, what they've put out in their public statements, they're even slower than that. There's also some variation between different manufacturers - it seems like they're extending their roadmaps, Let’s slow it down. We believe it’s because the investment required to keep the space going is very high.”

Still, competitive risks are high enough that these investments are inevitable. “The main way forward, the main multiplier, is to add more layers to the stack,” Rosmeulen said. "There's so little room to do XY shrink and shrink the memory holes. It's hard to do. Maybe they squeeze a few percent here or there, put the holes together, have less gaps between the holes, that sort of thing. But this Not the biggest gain. Density can only increase significantly at the current rate if you can keep stacking more layers."

Figure 4: 3D steps in NAND manufacturing.

Source: objective analysis

Further stacking seems reasonable, except for the inevitable problem at the heart of the whole process.

“The main challenge is etching, because you have to etch very deep holes with very high aspect ratios,” Rosmeulen said. "If you look at the previous generation there were 128 layers, which was a hole about 6, 7 or 8 microns deep, only about 120 nanometers in diameter, extremely high aspect ratio - or maybe a little higher, but not that much. Etch There are advances in technology that can etch deeper holes in one go, but you can't increase the etch rate faster, so if the process is dominated by deposition and etching, adding more is not cost effective. layers are no longer as effective as reducing costs.”

Etching is also just one of several steps. “In addition to etching, you also need to fill the hole evenly from top to bottom with a very thin dielectric layer,” said Synopsys’ Lin. "Normally, it's not easy to deposit layers of a few nanometers because of the chemistry of the wafer. Here, they have to go all the way down to fill up. There are subatomic layer deposition methods, but it's still challenging. Another big one The challenge is stress. If you build up so many layers, those layers are going to go through some etch/deposition/clean/thermal cycles, which can cause local and global stress because after you drill the holes, you need to do that throughout. A very deep trench is cut into the stack. It becomes a very tall skyscraper that is crumbling. If you start going through some wash or other process, a lot of things can cause two skyscrapers to collapse on each other. gains. And by putting so much material together and cutting different patterns, it creates global stress and causes wafer warping that the fab can't handle because the wafer has to be flat.

This is just the beginning. Remember, the etching is going through layers of different materials. "

Objective Analysis's Handy said Samsung's solution is to create extremely thin layers. “That’s great for the industry as a whole because everyone is using pretty much the same tools to create these things.”

There are also inherent functional challenges to the basic concept of flash memory. "There's an increasing reliance on error correction algorithms that require increasingly powerful ones to work with these devices," said Cadence's Greenberg.

The problem is that NAND flash devices don't have much intelligence built into them. “Typically, SSD happens on the controller side,” Greenberg explained. "The controller is sending commands to the NAND flash device and the NAND flash device will respond, but it doesn't have much intelligence. It just responds to the request, such as a block of data for a specific address. The NAND flash device will simply respond with that data block. But on the controller side you have to first error correct the received data, then determine if there is an unacceptable number of errors in the block, and then decide how to remap the block address space and put a different block. All these decisions happen on the controller side.”

Nonetheless, a world built of nanoscale skyscrapers has re-emphasized components such as ONFI controllers and ONFI PHYS and presented new challenges for designers.

“The number of tiers that a memory factory can produce makes the design verification issues for controllers that interface with these memories very complex—and they may not be that obvious. SSD controllers have to handle more memory channels. Connecting many pipelines with cross-border Connecting host interfaces that come faster and faster (but never fast enough) creates bottlenecks in very unexpected places," said Siemens' Whitehead. “Another design verification challenge is power. For a long time, most storage controllers were a low priority, but this has now transitioned into a critical function. Moving to smaller nodes will help, but is costly. The business model cannot tolerate it. Re-spin, not to mention long supply chain delays, have made it abundantly clear to senior management that storage’s growth momentum is even greater, requiring greater storage control in how we validate designs. processors, which can quickly consume your simulation and prototyping capabilities. Edge intelligence requires orders of magnitude more complex design verification. In-memory computing, such as CSD, requires testing new processor combinations, RTOS and HTOS to work with previously unseen. Loads mixed together.”

This is one of the reasons why people are so focused on verifying IP.

“Automation using this IP can quickly generate test benches, allowing design and verification teams to be up and running in minutes,” said Joe Hupcey, ICVS product manager at Siemens Digital Industries Software. “This level of productivity allows us to test the entire design. Architectural exploration to gain early confidence in the trade-offs chosen, while also establishing a framework for automatically tracking metrics—such as code, feature, and scenario coverage—to enable teams to measure their progress and have the authority to make sign-offs. Determine the data required. Finally, building on our expertise in the CXL/PCIe protocol, we see emerging standards such as Universal Chiplet Interconnect Express (UCIe) enabling teams to collaborate to quickly design and validate these massively scalable memory modules. plays a key role.”

In addition, Imec is exploring potential new structures for 3D NAND. It demonstrates what's known as a "trench architecture," a design variation in which the memory cell is part of the sidewalls of a trench and two transistors are located at opposite ends of the trench. Jan Van Houdt, Ferroelectrics Program Director at Imec, explains its value: "The 3D trench architecture has the potential to double the density compared to the gate-all-around (or cylindrical) architecture currently used."

However, he went on to point out some shortcomings. "There are two high aspect ratio (=challenging) etch steps instead of one, as well as the lower electric field in the tunnel oxide in the flash case. The second disadvantage does not exist when using ferroelectric FETs, which makes the trench The slot version is more attractive for iron than for flash memory.” The design is still in the prototype stage.

In 2016, experts noted that 3D NAND could run out of steam at or near 300 layers due to technical issues. This appears to have been replaced by cautious optimism today.

"[After SK Hynix's 238 layers] I expect the number of layers to increase at about the same rate over the next few years," IBM's Pletka said. "However, from a technology perspective, increasing the number of layers is challenging because of the high aspect ratio etching process, and also the capex is challenging because the time to make a chip increases with the number of layers. That's why we are going by fabricating Thinner layers, lateral scaling (e.g. placing vertical vias more densely) and using more efficient layouts (e.g. shared bitlines and logic scaling) will see new scaling directions (e.g. using split-gate architecture or storing more bits per cell). With these technologies, NAND flash storage density is expected to grow at a similar rate for at least the next 5 to 10 years.”

Others agree. "When people say we can't go beyond this number of layers, there's no physical limit," said Jim Handy, principal analyst at Objective Analysis. "In semiconductors, there are always people who say we can't do it. We can't do lithography below 20 nanometers. Now, they are working on 1 nanometer. Samsung talked about 1,000 layers. Maybe in 20 years we will laugh, we once thought That’s a lot.”

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