The next-generation transistor candidate is not silicon!

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementations to devices that work with silicon electronics, and may be used in high-performance digital electronics as well as radio frequency and sensing Application platform. The recent progress in materials, devices and technologies of carbon nanotube transistors is briefly reviewed. The most broadly impactful advances, from the development of single nanotube devices to aligned nanotubes and even nanotube films, are highlighted. There are still several hurdles to overcome, including materials synthesis and processing control, device structure design and transmission considerations, and further integration demonstrations to improve reproducibility and reliability; however, more than 10,000 devices have been achieved on a single functional chip. integrated.

A transistor is an electronic switching device that is capable of performing digital computations based on its on (binary 1) and off (binary 0) operations. In the early days of integrated circuits, it was clear that reducing the size of transistors would drive better chip-level performance, which is now known as Moore's Law. One of the most important dimensions of this scaling is the semiconductor channel length, which is the distance over which current flows, or the device is turned on and off as controlled by the gate electric field. Although original channel lengths were many micrometers in size, proposals to extend semiconductor channels to the limits of molecular size (a fraction of a nanometer) date back to the mid-1970s. Decades of research into electron transfer through conjugated organic molecules, thought to replace the silicon channel, have highlighted several important challenges for such molecular transistors. The most important issues include low stability and difficulties in efficient gating and forming reliable electrical contacts with molecules.

To match or exceed the performance of silicon electronics, it is clear that new channel materials must have similar stability. Among the molecules of choice, semiconducting single-walled carbon nanotubes (CNTs) have several advantages. Nested multi-walled carbon nanotubes are effectively metallic at room temperature and therefore have limited use as transistor channels. In this review, CNT will mean single-walled carbon nanotubes. Semiconducting carbon nanotubes consist of cylindrical shells of hexagonally arranged carbon about 1 nanometer in diameter. The electrons move only forward or backward, and the wave function wraps around the nanotube, forming a one-dimensional (1D) semiconductor with an energy band of several hundred millielectronvolts. These materials are stable in air and can be manipulated by a variety of processing methods commonly used in the semiconductor industry. Early demonstrations of field-effect transistors (FETs) by coating semiconducting carbon nanotubes on metal electrodes led to continued research activity with the goal of making reproducible, scalable and High-performance devices integrated into dense circuits.

The widespread interest in carbon nanotube semiconductors has also inspired intense and ongoing exploration of other nanomaterials, including semiconductor nanowires, 2D graphene, transition metal dihalogenates, and xenon. While there are a growing number of nanomaterial options, carbon nanotubes stand out for their stability, band gap, and excellent electrical and thermal properties that other candidates cannot match. Here, we review recent materials, device, and technology advances in carbon nanotube transistors, establishing the substantial promise and remaining challenges of this molecular transistor. Progress in this area will be related to the most important potential applications of carbon nanotube transistors, as shown in Figure 1. The two most prominent potential applications are high-performance (HP) computing chips and thin-film transistors (TFTs) for display backplanes and the Internet of Things (IoT); Table 1 summarizes some target performance metrics for these applications.

cost and complexity

Figure 1 shows the wide range of potential applications for carbon nanotube transistors. Device performance versus cost and complexity for some of the most important potential applications of carbon nanotube transistors is illustrated. Applications range from microscopic thin film devices (e.g. printed electronics, biosensors) to 3D integrated BEOL devices (e.g. heterogeneous 3D layers integrated onto silicon CMOS) and scale high performance (HP) FETs [e.g. low voltage very large scale integration (VLSI)] , whose performance improvements correspond to increased integration costs and complexity. L ch , channel length.

Table 1: Several target metrics for two prominent carbon nanotube transistor applications. Values ​​are approximate based on achieving optimal performance. It is worth noting that while some of these goals have been achieved, one of the most important challenges is achieving them simultaneously (e.g., high pass-through current with low under-threshold swing, which is a measure of how much gate voltage is required to modulate the current). High-performance FETs are used in applications such as central processing units (CPUs) in servers, and TFTs are thin-film transistors used in display backplane electronics.

Harnessing the advantages of carbon nanotube semiconductors requires overcoming several materials science hurdles. Just as silicon must be purified and doped to become a useful channel material, synthetic carbon nanotubes can be either metallic or semiconducting and must be purified to be semiconductors only for use in transistors. Whether carbon nanotubes are metallic or semiconducting depends on how the hexagonal lattice is packed into the tube. This structure is most easily observed by rolling rectangular portions of the sp2-bonded hexagonal carbon lattice of atomically thin graphene ^into a one-dimensional cylinder with a diameter of about 1 nanometer and a length of 10 ^to 10 ^nanometers . The vector that defines the rectangular cross-section relative to the width of the graphene lattice is often called the chiral vector and ultimately determines the diameter, helicity and conductivity of the carbon nanotube.

In addition to specifying the physical structure of the carbon nanotube, the chiral vector imposes explicit quantum mechanical boundary conditions on the electronic band structure, which means that for random tube closure, ~33% of the carbon nanotube chirality is metallic, ~ 67% are semiconductors. Furthermore, in semiconductor chirality, the band gap is approximately inversely proportional to the carbon nanotube diameter. Since carbon nanotube transistors require semiconductor channels, preferably with well-defined and consistent band gaps, the ability to scalably synthesize and isolate carbon nanotubes with atomically precise chiral vector control is the ultimate in high-performance carbon nanotube integrated circuits. Target.

The synthesis method of carbon nanotubes is to introduce carbon-containing raw materials and metal catalysts (usually iron or nickel) into a growth chamber, and add energy through heat, light or plasma excitation in the growth chamber. Because carbon nanotube growth typically occurs at temperatures where these catalysts undergo extensive recombination, it is difficult to control the chiral vector, and a range of carbon nanotube diameters and two electron types have been produced; in order to control the chirality of carbon nanotubes, it has been It took a lot of effort. These methods include the use of refractory catalyst particles such as W-Co alloys with well-defined sizes and shapes that remain structurally unchanged at growth temperatures and therefore can drive predictable nucleation of targeted carbon nanotube chirality (Figure 2A), Add a molecular seed whose structure closely matches the chirality of the targeted carbon nanotube, or unfold the carbon nanotube itself as a seed in Nanotube Cloning. While customized catalysts or seeds help control synthesis outcomes, many other growth parameters also play a role, including temperature, pressure, flow rate, and applied electric field—so growth optimization requires searching a broad parameter space. To accelerate this exploration, autonomous growth using closed-loop iterative experiments promises to rapidly identify synthesis conditions that minimize carbon nanotube structural polydispersity.

Since optimized carbon nanotube growth procedures still lack sufficient monodispersity for wafer-scale transistor applications, post-synthesis separation methods are needed to sort the grown carbon nanotubes by diameter, chirality, and electron type. Fortunately, the size and shape of carbon nanotubes are comparable to biological macromolecules, allowing many carbon nanotube separation methods to be modified from already developed biochemical separation methods. In density gradient ultracentrifugation (DGU), carbon nanotubes are first dispersed and coated with a mixture of surfactants that respond to different carbon nanotube separation targets including chiral vector, chiral chirality, electron type, and diameter) are selective and then separated by buoyant density in the water density gradient. Although DGU is sufficiently scalable to be commercially viable, other strategies in biochemistry have also been vigorously developed, including gel chromatography and dielectrophoresis. The latter approach has the added benefit of being able to assemble CNTs in alignment between pre-patterned electrodes.

Methods from polymer chemistry have also been used to isolate carbon nanotubes, including aqueous two-phase extraction and structural identification of polymers that wrap the nanotubes to selectively disperse and target carbon nanotube chirality (Figure 2B). In all cases, the purity of semiconducting carbon nanotubes has reached the detectable limit of optical spectroscopic characterization (~99.9%) and is beginning to provide sufficient monodispersity for many carbon nanotube transistor applications. The ultimate goal for high-performance digital transistors is to achieve 99.9999% pure semiconducting carbon nanotubes (see Table 1)—the higher the purity, the better the corresponding performance. Additionally, any molecular packaging (such as surfactants or polymers) should ideally be completely removed after carbon nanotube deposition, as this will create harmful residues that can hinder electrical contacts, gates, and gates in carbon nanotube transistors. control efficiency and transmission.

Transistors also require electrical contacts, doping, and dielectrics. Since contacts from commonly used metals (e.g., Au, Pd) tend to produce Fermi level alignment near the valence band of carbon nanotubes, p-type behavior resulting from hole injection is easily achieved in carbon nanotube transistors. However, the complementary requirements of p-type and n-type transistors in digital circuits mean that controlled n-type implantation and/or doping is required.

Electron-donating adsorbents, such as organo-rhodium compounds, combined with atomic layer deposition encapsulation layers, can produce highly stable n-type carbon nanotube transistors (Figure 2C). Charge-selective contacts based on metal work functions, such as p-type implanted Pd and n-type implanted Sc, also enable complementary CNT transistors. In addition to metal selection, interface material considerations and overall contact structure also play a role (see Figure 2D for an example of an end-bonded contact structure using Mo). The extension area of ​​the metal oxide semiconductor field effect transistor (MOSFET), between the source or drain and the gated semiconductor channel, requires stable doping and a well-controlled doping level, which is between the series resistance and the parasitic capacitance. Optimizing the trade-offs between nanotubes—a feat that has yet to be reliably accomplished in carbon nanotube transistors. For the gate dielectric layer, specific materials such as Y2O3 exhibit near-ideal performance with high dielectric constant κ and conformal dielectric coating on CNTs after oxidation of deposited yttrium . A more traditional approach uses atomic layer deposition of a bilayer dielectric of AlO and HfO , resulting in transistors with gate lengths of 10 nanometers and gate leakage currents comparable to state-of-the-art Si transistors. After integrating all these optimized materials, carbon nanotube transistors have been shown to exceed the performance of existing silicon integrated circuit technology, as will be discussed in subsequent chapters.

Figure 2: Examples of materials for high-performance CNT transistors include synthesized CNTs, purified CNT mixtures, doping strategies, and contact metals.

(A) Templated carbon nanotube growth with targeted chirality using refractory W-Co nanocrystal catalyst. CVD, chemical vapor deposition; SWNT, single-walled nanotubes.

(B) Selective polymer dispersion enables scalable separation of target carbon nanotube chirality from growing polydisperse mixtures, as verified by absorption spectroscopy, as shown on the left; synthesis of sorted carbon nanotubes is shown on the right bottle photo. E11 and E22 are absorption peaks; SFM, shear mixing.

(C) Stable n-type CNT transistors can be achieved using electron-donating organic rhodium compounds encapsulated in atomic layer deposited aluminum oxide. Black is the CNT layer, orange is the dopant layer, and red is the seed layer for dielectric growth.

(D) When the reaction forms terminal carbides, the contact length (Lc) of the molybdenum and carbon nanotube transistors can be reduced to less than 10 nm in size while maintaining efficient charge injection.

The initial focus of carbon nanotube transistor research was on using individual carbon nanotubes as channels (see Figure 3, a and B) and demonstrating ballistic transmission and operability of digital circuits. While devices with single nanotube channels remain of interest for sensing applications, they are no longer considered suitable for digital or radio frequency (RF) electronics due to the need for higher current flows compared to the higher current flows provided by a single nanotube. Although the current-carrying capacity of carbon nanotubes is staggering [~10 ⁹ A cm ^{− 2} ], they are only about 1 nanometer in diameter and generate only about 10 milliamps of current per carbon nanotube. Therefore, recent work has mainly focused on having multiple CNTs in the channel.

Ideally, the carbon nanotubes in the transistor channel would be perfectly aligned in a parallel array with a spacing of 2-5nm, similar to how silicon fins are arranged in modern transistor technology (finfets). Implementing such arrays remains a challenge. If the carbon nanotubes are too tightly packed (or bundled), there will be problems with crosstalk (electric field shielding) and efficient gating. If the carbon nanotubes are too far apart, the current density (current per transistor width) will be insufficient. For digital systems with high densities of carbon nanotube transistors, changes in the spacing between carbon nanotubes can also adversely affect overall energy, latency, and noise margins.

Recent progress is encouraging, including a small-scale demonstration of using DNA-directed assembly to control carbon nanotube spacing to 10 nanometers. There are also wafer-scale high-throughput strategies using various forms of solution-phase assembly (also known as size-limited self-aligned or liquid crystal interface assembly), achieving a pitch of 20 nm in one report (Figure 3, C and D), a pitch of 5 to 10 nm was achieved in another report. The main differences between the two studies are the polymer used to encapsulate the CNTs and the solid-phase technology used to deposit the CNTs onto the substrate array. Still, these methods require further work to eliminate unnecessary residues during processing of the solution stage and achieve more consistent, controlled alignment (without bundling) in all directions at even spacing.

Because of the difficulty in achieving aligned arrays with controllable spacing, some researchers have used unaligned carbon nanotube networks or films (Fig. 3, E to H). Although these misaligned films are detrimental to carrier transport and to contacting and gating the nanotubes, misaligned carbon nanotube networks enable high performance in nanoscale transistors.

Furthermore, carbon nanotube films can be deposited by using printing techniques, including roller and direct writing methods (Figure 3H), which makes them attractive for TFTs. These larger TFTs (on the order of tens of microns) have a different application space than high-performance nanoFETs, including sensors, flexible electronics, IoT, and display backplanes. For TFT applications, CNT films compete well with existing semiconductor options such as organics and polymers, metal oxides and low-temperature polysilicon (LTPS).

When carbon nanotube films were used in FETs with nanoscale channel lengths (<100 nm), most nanotubes bridged the entire channel, even though they were not perfectly aligned (Figure 3F). At the microscale length of TFTs, the nanotubes in the film channel are not large enough to traverse the channel, but instead operate as a permeable network in which electrons travel from carbon nanotube to carbon nanotube during transport from source to drain (Figure 3G ). Compared with long-studied organic semiconductor TFTs, CNT-TFTs have higher mobility (10-100cm ² V ^{− 1} s ^{− 1} ) and stability under bias, in air, or both.

In addition to the density and arrangement of nanotubes in the channel, the gate structure of carbon nanotube transistors has advanced in many ways. For nanoscale FETs, the main goal is to maximize gate control of the carbon nanotube energy band in the channel, which is achieved through strong gate coupling, often expressed as a small scale length λ. The scale length depends on the gate geometry as well as the thickness and dielectric constant of the gate dielectric and semiconductor channels. A generally accepted approximation is that channel lengths greater than 3λ will ensure that harmful short channel effects are avoided.

Due to their inherent small size, CNTs offer advantages for massively scalable devices. Although it is ideal for FETs to have a gate-full geometry to minimize λ, and demonstrations of carbon nanotube gate structures have been reported, studies have shown that neither bottom gate nor top gate Geometries, channel lengths well below 10 nm (as short as 5 nm) can be achieved. Although the gate geometry is different for TFTs, it is not critical and is mainly limited by the gate dielectric material and application requirements.

For high-ratio carbon nanotube transistors with small footprints, not only do the channel lengths need to be on the nanometer scale, but the source and drain contacts also need to be of minimal size while still providing efficient ohmic charge injection. Palladium contacts reach the quantum limit of 6.5 khm per carbon nanotube at 10nm contact length. In p-side contacts, the metal sits on top of the carbon nanotube without any chemical bonding, although this is required at higher yields and reproducibility. to fulfill. Additionally, the edge contact structure would provide ideal scalability and has been verified by reacting with carbon nanotubes to produce carbide end-bond contacts with contact lengths below 10 nm (Figure 2D). Regardless of their geometry, contact with carbon nanotubes is a major factor in determining overall performance, and the combination of materials, structure, and processing must be further improved to produce highly consistent and low-resistance p- and n-type carrier injection. touch.

Although many applications can benefit from the properties of carbon nanotubes, digital logic applications have received the greatest attention (Figure 4) because of their potential to surpass existing Si technology in performance and energy efficiency. This typical high-performance device comes from aligned arrays of carbon nanotubes that can achieve high on-state current at relatively low voltages (Figure 4, A to C). As shown in Figure 4D, at the 2 nm technology node (EDP, or switching energy), gated omnipotent carbon nanotube transistors doped with extended and multilayered high-density carbon nanotubes are expected to show up to 7 times the energy delay product (EDP) benefit, which is the product of an on-off cycle time and power consumption and is a measure of energy efficiency). As mentioned earlier, due to their ultra-thin structure (~1nm), carbon nanotube transistors offer excellent electrostatic control even over the gate length, limited only by direct source-drain tunneling. Parasitic capacitance is a key factor in speed and energy efficiency, accounting for 70% of the total capacitance of modern silicon transistors. Due to their ultra-thin structure, carbon nanotube transistors have very low parasitic gate-source or gate-drain capacitance. These two key properties of CNTs, along with high transmission and injection speeds, are the physical basis for high-performance, energy-efficient digital logic.

Figure 4: High-performance carbon nanotube transistors for digital logic applications

(A and B) Subthreshold (A) and output characteristics (B) of CNT transistors fabricated from aligned arrays of approximately 150 CNTs per micron, enabling on-state currents >1 mA μm ^{− 1} . I ds , drain current; V ds , drain-source voltage; V gs , gate-source voltage.

(C) Device schematic of silicon nanosheet transistor and carbon nanotube aligned array transistor with two stacked channels.

(D) Projected energy versus frequency Pareto curves for Si nanosheets and CNT transistors at the 2nm technology node of the inverter ring oscillator.

As mentioned previously, many of the basic building blocks of carbon nanotube transistor technology have been demonstrated. At the circuit or system level, a fully functional static random access memory (SRAM) array, a monolithic 3D imager, and a 16-bit RISC-V (where RISC is reduced to an instruction set computer) processor > 14,000 transistors ( Figure 5B) is made entirely of CNT transistors. Additionally, wafer-scale manufacturing of carbon nanotube transistors has been demonstrated in foundries using 200 mm wafer processing technology (Figure 5A). Fabricating and designing carbon nanotube transistors using the same tools and infrastructure as commercial semiconductor technology helps lower the barrier to mass production of carbon nanotube devices.

Figure 5: Wafer-scale and three-dimensional integration of carbon nanotube transistors.

(A) 200 mm silicon wafer with carbon nanotube transistors processed at a commercial silicon foundry. The lower left corner shows an image of a single die or chip in a wafer, and the lower right corner shows a schematic of a carbon nanotube transistor structure. D, drain; G, gate; K, relative dielectric constant; S, source.

(B) Optical image of a RISC-V processor implemented with a CMOS carbon nanotube transistor (RV16X-NANO) showing the carbon nanotube circuit (false colors indicate different metal layers) and a single carbon nanotube device (CNT High magnification image of details highlighted in yellow).

(C to E) Image and schematic of a 3D N3XT chip integrating CNT transistors and RRAM memory layers on top of silicon logic (C); cross-sectional TEM image showing bottom Si logic layer, RRAM memory layer and two CNT transistor layers [Carbon Nanotube field-effect transistors (CNFETs), logic and sensors] (D); and scanning electron microscopy images (scale bar, 500 nm) of top-layer CNT circuitry and devices in a three-dimensional N3XT chip (E).

At the individual device level, recent studies have shown short gate lengths (10nm), complementary p-channel and n-channel devices with near-ideal subthreshold swings for single CNT transistors, and for devices with 50 CNTs per micron. The density of aligned CNTs has high on-state current per width. In the near future, it will be possible to integrate the following elements (shown separately) in a single device demonstration: gate-all-around geometry, >250 nm/micron in highly consistent arrays, 3nm oxide dielectric (target oxide Capacitance = 2.94 × 10 ^{− 10} F m ^{− 1} ), sub-10-nm p-type contact resistance of 6.5 per kiloohm, sub-10-nm gate length, multiple stacked interchannel layers, and doped source or drain extensions . This mosfet-like carbon nanotube structure with a 35nm contact gate pitch and 20nm active width is expected to perform well beyond Si transistors in 2nm node logic technology.

Future semiconductor chips will go beyond the miniaturization of two-dimensional devices and will be replaced by active devices with three-dimensional layers. Since 3D logic device layers must be thin and fabricated at temperatures compatible with back-end-of-line (BEOL) wiring layers (typically <400°C), CNT transistors are particularly suitable for 3D integration due to low device fabrication temperatures and thin device layers. Since the first demonstration of an all-carbon nanotube transistor computer about a decade ago, progress has been made not only in the level of integration, but also in the diversity of devices and the maturation of the technology from university laboratories to industry.

A four-layer monolithic integrated chip consisting of a silicon transistor layer, a carbon nanotube transistor memory readout circuit layer, a resistive switching metal oxide random access memory (RRAM) layer and a carbon nanotube transistor sensor layer on top illustrates monolithic integration benefits (Figure 5, C to E).

This 3D chip can process information from sensors to memory cells to transistors in parallel at terabytes per second. Another example is an end-to-end brain-inspired ultra-dimensional computing nanosystem that is highly effective for cognitive tasks such as language recognition, which is achieved through monolithic 3D integration of CNT transistors and RRAM, using BEOL interlayer vias to enable computing Fine-grained and dense vertical connections between tiers and storage tiers. The carbon nanotube transistor manufacturing process is not only shown on a full 200mm wafer, but also features 3D integration with RRAM.

Although digital electronics remain the main focus in this field, CNT transistors also hold great promise for high-frequency radio frequency transistors. Many of the material and device requirements for digital carbon nanotube transistors also apply to radio frequency electronics, with the requirements for semiconductor purity relaxed and the need for high transconductance and linearity enhanced, which translates into low distortion when amplifying the signal. Recent advances in radiofrequency carbon nanotube transistors made from arrays of nanotube arrangements show that the transistors can operate at frequencies up to hundreds of gigahertz, have attractive low power consumption and high versatility, and can be integrated on a chip system application.

The purification ability of solution phase dispersion of semiconducting carbon nanotubes also enables printing into thin film devices (Figure 2H). Many reports indicate that fully printed CNT-TFTs can be used in digital logic circuits, illustrating the ability of these devices to provide computing functions. However, given the low cost of conventional node silicon transistor technology, the likelihood that printed CNT-TFT circuits will be widely used is low. Even more encouraging is the use of printed CNT-TFTs for backplane control of displays or for custom biosensing systems. Recent research has also revealed the recyclability of carbon nanotube films, showing promise for fully printed paper-based electronic systems in which all core materials can be recycled and reused.

Advances in materials are expected to be central to future advances in carbon nanotube transistors. Improving the purity of semiconducting carbon nanotubes is critical for all device use cases. In this regard, one of the biggest obstacles to reducing metallic carbon nanotube impurities to parts per million or billions concentrations is the lack of high-throughput analytical methods for detecting metallic carbon nanotubes at ultra-low concentrations. For carbon nanotubes, most high-throughput optical detection methods (such as photoluminescence spectroscopy) are less sensitive, if not completely insensitive, to metal species. In fact, the only sure way to quantify ultralow concentrations of metallic carbon nanotubes is to make large arrays of individual carbon nanotube transistors and then electrically probe them one by one to look for shorts. This method is very time-consuming and will only get worse as semiconductor purity increases. Therefore, most carbon nanotube separation methods are only optimized to the detection limit of optical spectroscopy (99.9%).

Another unresolved issue for semiconducting carbon nanotubes is the need for a scalable and sustainable manufacturing method to produce ultra-high purity semiconducting carbon nanotubes in sufficient quantities to satisfy the potentially large market, including not only high-performance integrated circuits , also includes high-volume printed electronics. Most solution-based separation methods present no fundamental barriers to scalability, but the throughput of these processes is ultimately limited by the quality of the input feedstock. To improve the yield of downstream separations, synthesis processes need to be improved to minimize impurities and maximize the purity of semiconductors with narrow nanotube diameter distributions. One tempting option is to improve cloning technology to the point where iterative isolation and amplification can be achieved in a manner similar to polymerase chain reaction (PCR) in biochemistry.

Ultimately, growth conditions encompass such a large parameter space that efficient methods for searching and identifying optimal growth conditions are needed. Emerging artificial intelligence and machine learning optimization methods combined with high-throughput experimental screening hold promise for next-generation integration efforts. Similarly, the discovery, optimization, and integration of many other materials (including dopants, contacts, gate electrodes, and dielectrics) in carbon nanotube transistors can also be accelerated by machine learning coupled with high-throughput experimental screening.

Although much has been learned about building interfaces to carbon nanotubes, including gate structures and contacts, challenges remain. The role of materials selection and purification (discussed previously), fabrication methods, and doping control continues to be elucidated in numerous reports. In fact, one of the most important challenges moving forward is determining which combination (among the thousands of reported materials and processes) is best to use. More systematic studies are needed to explore the impact of certain contact and cap material configurations on device performance, yield, reproducibility, and stability. For example, carbon nanotube channels extend to lengths below 10 nanometers in various configurations, but it is unclear which device architecture is superior (e.g., top gate vs. full gate, side contact vs. edge contact) and which performs best The option also has a manufacturing process that is compatible with the associated manufacturing of complementary metal oxide semiconductor (CMOS) fabs. Most contact formation processes with metals rely on uplift, which is considered a non-scalable process, and uplift-free alternatives also tend to rely on slow patterning processes.

Contact length scalability requires further consideration and is a parameter as important as overall scaling of the transistor gate length. Some studies show severe degradation at contact lengths below 30 nm, while others show lighter degradation at corresponding lengths, but high yields have not yet been achieved. This contact length scaling challenge is common to all transistors, but discovering a solution that allows for large scaling of contacts without degrading the device would be a key advance. End bonding or edge contact offers one such possibility, although further work is needed to reduce processing temperatures and understand shipping and performance limitations. Furthermore, achieving similarly high-quality and scalable contact n-type carbon nanotube transistors remains to be solved.

For TFTs from carbon nanotubes, much of the knowledge gained from nanoscale FET devices is applicable. The most important exception is that TFT technology should ideally be compatible with large substrate sizes and have very low cost. Since one of the major applications of TFTs is in display backplanes, the materials and processes should be scalable to large panels. While device-level performance and size are important, TFTs relax restrictions and put more emphasis on manufacturing costs because these devices will be used in commodity applications (such as backplanes) or single-use applications (such as IoT). Recent demonstrations of recyclable printed carbon nanotubes-TFTs on paper substrates suggest sustainable measures. It is crucial to improve the yield and stability of carbon nanotube-TFTs, especially the role of tube-tube contacts in the permeable network.

There are many remaining obstacles to realizing carbon nanotube transistor technology that meet the needs of high-volume production and will require concerted efforts from academia and industry to overcome. Regarding semiconducting carbon nanotube purity, although the highest purity is still the ideal purity for EDP, logic design techniques can be used to relax the requirements for some applications by about 100 times (from 99.9999 to 99.99%) without adding additional processing steps or redundancy.

For high-performance digital systems, device variations play an important role in determining the overall EDP and noise margin of the system. Sources of variation unique to carbon nanotubes include carbon nanotube density and pitch (the distance between carbon nanotubes in a multi-carbon nanotube transistor), the carbon nanotube band gap (determined by chirality and diameter), and the response to surrounding random fixed charges. Extreme sensitivity (this is why carbon nanotubes are ultra-sensitive sensors).

The transistor width of logic technology (perpendicular to the direction of current flow) is on the order of 20 to 40 nanometers. When the carbon nanotube density is 250 CNTs per micron, there are only 5-10 CNTs in the channel; therefore, changes in carbon nanotube density and carbon nanotube spacing will result in substantial changes in current drive.

Design solutions that reduce this variation are essential as part of the co-design process for technology development. For example, changes in the band gap of carbon nanotubes are directly translated into changes in out-state leakage current through threshold voltage and band-to-band tunneling of the drain. Band-to-band tunneling leakage scales exponentially with the band gap and sets the minimum achievable leakage current, which is the boundary between stateful and stateless leakage currents exchanged by adjusting the threshold voltage. Direct source-to-drain tunneling current also depends exponentially on the band gap and sets limits on gate length scaling. The choice of carbon nanotube diameter (band gap) faces the same trade-offs as other FETs. Small bandgap CNTs have lower effective mass and higher on-state current, while large bandgap CNTs have lower tunneling state leakage current and can further reduce the gate length and maintain higher operation at high speeds. Voltage. Given the target computing workload, the optimal choice must be application dependent and must be co-designed.

Although the carbon nanotube transistor inherits all the limitations of the MOSFET (electrostatic and transport physics) and has all the challenges of low-dimensional channel materials (contacts and surfaces without dangling bonds), it also retains all the advantages of the FET, including good The circuit or system design ecosystem and mature manufacturing technology have further potential in increasing the number of devices and connecting chips integrated in three dimensions. These benefits are expected to eventually outweigh all limitations, as the power of presence and scalability in three dimensions cannot be underestimated. Between the opportunity for high-performance digital logic with the potential for 3D integration and the possibility of printing and even recyclable thin-film electronics, carbon nanotube transistors deserve renewed or even redoubled efforts from academic, government, and industrial contributors. These molecular transistor technologies are within reach, but only if the scientific and engineering communities can overcome the remaining challenges.