Advanced packaging: Intel leads TSMC in this area

Latest update time：2022-01-19

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In previous reports "The Strongest Popular Science of Advanced Packaging" and "Interpretation of Advanced Packaging Technology by Giants" , we introduced the necessity and basic overview of advanced packaging and the main types of key logic products, memory and image sensor packaging modes. In this article, we will discuss thermocompression bonding (TCB) and the three major tool manufacturers in this field, ASM Pacific, Kulicke and Soffa, and Besi. Thermocompression bonding is an evolution of the standard flip chip process, but involves many advantages and disadvantages, which we will also discuss here.

Thermal Compression Bonding (TCB) is used in all current forms of HBM memory. Most of Intel’s packaging technology also uses TCB. Intel has bet very heavily on this technology as a driver of their packaging needs, and TSMC has not followed suit at all. We will discuss how this technology and Intel’s unique role in its development has enabled them to become a leader in advanced packaging, but we will also discuss some of the shortcomings. Intel is looking to continue spending hundreds of millions of dollars in orders on TCB tools for expansions in Arizona, New Mexico, and a new $7 billion packaging facility in Malaysia. We will start by explaining the technology, Intel’s primary role in its development, and finally the tool ecosystem.

To understand the advantages of TCB, we must first talk about the disadvantages of flip-chip packaging. As described in " Interpretation of Advanced Packaging Technology of Giants" , the standard flip-chip process starts with the deposition of flux or non-conductive paste. The chip placement tool then accurately places the chip on the substrate, interposer or carrier. This is done in a batch process, so many packages can have their bare die placed at once. The placed die set then enters the reflow oven, which is also a batch process. Dozens, hundreds or even thousands of packages are placed in the oven and heated to a temperature that melts the solder to complete the bonding, and then continue with subsequent steps such as removing flux residues and bottom filling.

This process is very fast, but it also has some major drawbacks. The biggest issue has to do with the coefficient of thermal expansion (CTE). Because the entire package is made up of many different materials, heating in a reflow oven causes these different materials to expand at different rates. Below we'll use an example, although it's not the best analogy, it still makes sense. If you've ever baked a pie, you know that the pie crust and the pie filling do not expand at the same rate. If you're not careful about a few different factors, your filling will end up boiling over the top layer of the crust and making the crust soggy.

As the die and substrate expand and cool, differences in CTE can cause warping. Additionally, because the die is placed and re-soldered, the solder balls may not make perfect contact with each copper pad, causing chip gap variations. Finally, the die may not be placed completely flat. Over time, these small issues can accumulate and lead to early failures or worse electrical performance.

The industry was left to look at many of the original passive interposer technologies. AMD’s Fiji-based GPUs had very high failure rates because the process did not produce a perfect bond and ultimately thermal cycling caused the product to not work properly. These reliability issues have improved over time as TSMC and ASE/SPIL have learned how to do interposer-based packaging, but they have not been completely resolved. These issues are still common in environments where the temperature is unstable and the package is frequently cycled between high and low temperatures.

Coming to thermocompression bonding. Instead of placing the chips in a batch process and shipping the entire assembly to a reflow oven, we use a single tool to place individual chips, apply pressure, and heat them to reflow the solder balls. This solves several major issues with standard flip chips. Heating is done from the top of the chip, so only the chip and C4 solder connections heat up. This avoids substrate warping issues. The force ensures an even bond with no gap variation or tilting. Finally, when the force is applied, it is accompanied by rapid vibrations that break up metal oxidation on the copper pads and solder balls. A virtually void and contamination free bond.

TCB achieves better electrical characteristics at the same IO pitch. TCB allows IO pitch to scale to smaller sizes. TCB also enables thinner chips and packages. The latter is why HBM uses TCB and why Huawei is trying TCB in the mobile chip market. TCB may seem like a completely better technology than the standard flip chip process flow, but this ignores one major factor.

Looking at cost, an advanced TCB tool can place 500 to 1,000 dies per hour and costs about $1.25 million. On the other hand, an advanced flip chip die placement tool can place 3,000 to 10,000 dies per hour and costs about $450k. These numbers vary widely, depending on the trade-off between accuracy and throughput and the various features that may come with the tool, but its obvious that the throughput for standard flip chips is much higher. Reflow ovens are very cheap and can handle the output of many placement tools, so the cost is not worth worrying about.

What is curious is that Intel has close to 300 TCB tools, and double that number at the packaging facility in Malaysia. Those 300 tools far outnumber Intel’s advanced packaging uses. Intel uses TCB in many non-advanced packaging applications where a standard flip chip process is a good fit.

SemiAnalysis spoke privately with an Intel packaging engineer, and the reasoning is interesting: Given Intel’s large share of high-power and high-margin applications, yield losses and reliability issues far outweigh the negligible amortized cost per unit of packaging tools.

Additionally, these tools offer a lot of flexibility in terms of package type. Intel can use the same tools for standard packages, 2.5D packages, and advanced 3D packages. The image above is from der8auer and shows an Intel Sapphire Rapids server CPU with multiple pitch sizes. The EMIB has a pitch of 55 microns, and the rest of the die-to-package connection has a pitch of 100 microns. While this is theoretically possible without TCB, it is much easier to implement in the real world given the differences in pad and solder cap sizes.

The capabilities of TCB really started to shine when Intel moved to Foveros Omni. We discussed the technology in the aforementioned article, but the copper pillars and ODI die made Foveros Omni nearly impossible to package using a standard flip-chip process. The first Foveros Omni product will be Intel’s Meteor Lake, a mass-market client architecture designed for 5W SOCs all the way up to high-powered desktops. Despite containing many dies, Omni enables significant manufacturing cost savings, selecting the best process node for the IP and minimizing die size for high yields. The package is available in a variety of bump pitches of 130 microns, 100 microns, and 36 microns. Advanced 3D logic packaging isn’t just for high-performance applications.

Meteor Lake Test Package

TSMC, Samsung, and many others would not be able to do this packaging unless they invested heavily in TCB. Intel has been co-developing TCB tools for over a decade, so it would be difficult for competitors to immediately switch to this technology. TSMC’s InFO uses a standard flip chip flow, while potentially being a more expensive packaging technology due to the more expensive substrate. TSMC does not have advanced packaging, but rather is on a commodity standard ABF substrate, which hinders how far they can drive advanced packaging down in terms of cost. At the same time, InFO does have some of the key advantages we discussed in Part 2, which are related to complex routing within the RDL and not requiring the use of silicon wafers.

Hybrid bonding has capabilities beyond anything flip-chip TCB can offer, but the technology operates at a completely different point on the cost and performance curve, which undermines its ability to increase production in the medium term. This will be discussed in the future.

Intel’s support for TCBs allows them to create optionality around various IPs and manufacture many different blocks at many different nodes without much loss in die-to-die connectivity. The details of the strategy on the design side are discussed in this article on Intel’s TSMC wafer supply agreement.

TCB has also been adopted in HBM applications. HBM dies need to be very thin. The picture above only has 4 stacks, but as the industry expands to 8 stacks and even more, Samsung, SKHynix and Micron must use TCB. In SKHynix's upcoming 12-stack HBM3, the requirements for die thinness have become so extreme that each die has been thinned to 30 microns. The bump pitch is also very dense. The only way to enable HBM stacking at present is to use TCB technology, but the industry expects that more exotic packaging forms such as hybrid bonding may be used.

Since TCB is the best technology for packaging extremely thin chips, TCB has also been experimented with in mobile phone applications in flagship devices using OSAT and IDM packaging. Samsung, Qualcomm/Amkor, and Huawei/ASE are using TCB in some applications related to package-on-package (PoP) DRAM. OSATs are starting to order more and more TCB tools, but the largest orders continue to come from Intel and its custom co-developed TCB platform. The important thing to note about these other use cases is that they are not the same as Intel’s tools, and they are not designed for high power or high performance applications.

The market between ASM Pacific, Kulicke and Soffa and Besi is very active for TCB and each excels in different areas. This results in each having their own niche. The order book is rising significantly but the three are not in unison due to the niche they each occupy.

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