The world before FPGA came into being
Latest update time：2021-12-31 17:56
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In 1981, I (on behalf of this author) went to Boulder, Colorado to start my “career” designing workstations at Cadnetix. In fact, in the early years, the top computer-aided engineering (CAE) vendors at the time, such as Daisy Systems, Mentor Graphics, and Valid Logic (I call them DMV), were all founded in 1981, just like Cadnetix, and each developed a proprietary CAE software suite. From 1982 to 1985, the five proprietary Cadnetix workstations I helped design were all based on the Motorola 68000 microprocessor series (68000, 68010, and 68020) running a proprietary, stripped-down version of Unix (which I privately called “Eunuch” as an inside joke).
Daisy's CAE software is mainly used for logic design and can run on the Daisy proprietary version of Unix, "Daisy-Dnix", and the "Daisy Logician" proprietary workstation, and can also run on the later Mega Logician. Mentor's CAE software is mainly used for IC layout and PCB design. It can run on the early Apollo DN100 workstation based on Apollo Aegis, and can also run on the later Apollo/Domain operating system. Valid Logic Systems developed a proprietary version of the Unix operating system schematic capture software on the ScaldSystem proprietary workstation. (Valid was originally called SCALD because it was established by the founder of SCALD ("Structured Computer-Aided Logic Design"), a set of tools developed by Lawrence Livermore National Laboratory to support the design of the S-1 supercomputer.) Valid's other tools for logic simulation, static timing analysis, and packaging run on DEC's VAX.
In fact, by 1981 or so, a whole host of companies had been formed. Sun Microsystems was founded in 1982, and it was destined to be the 800-pound "gorilla" workstation. All these design workstations, plus DEC's VAX and the slew of minicomputers designed by its competitors, created a perfect market for a lot of early programmable logic. You needed fast ways to develop the usual logic (address decoders, state machines, etc.), as well as the fancy memory management hardware required for Unix systems. Eventually, microprocessor vendors added this memory management hardware to their products. But in the early 1980s, you had to do it yourself.
During this period, the two main methods of designing logic were to use TTL chips or, if there was enough capacity, custom chips (custom chips are what we now call ASICs, but that term had not yet been invented). Large numbers of TTL chips took up a lot of board space and were very power hungry. But custom chips were difficult to design, very expensive in terms of NRE, and took months out of the design cycle.
In order for engineers to quickly design, build, test and modify logic, the demand for field programmable logic devices continued to grow. Semiconductor suppliers also began to realize that this was a market opportunity. First came the field programmable logic array (FPLA), then PAL, GAL and CPLD. In 1985, FPGA finally appeared at the top of the programmable logic food chain.
Tracy Kidder's 1981 bestseller, The Soul of the New Machine, vividly describes how design engineers used programmable logic in the late 1970s and early 1980s. In 1982, the book won the National Book Award for Nonfiction and the Pulitzer Prize for General Nonfiction, and became one of the best sales tools for MMI (monolithic memory).
Kidder's book describes the development of the Dec VAX competitor, the Eclipse MV/8000 minicomputer introduced by Data General in the 1980s. Its logic design was largely based on MMI's PAL (Programmable Array Logic), which plays a major role in the book. To be honest, I don't know how a book about PALs and systems engineering became a national bestseller. I could have written an award-winning bestseller if I had been asked to write it - but it's too early to talk about PALs. The story probably starts with PROMs, and maybe even earlier.
Field programmability has been an important aspect of integrated circuit design almost since the beginning of integrated circuit development. The first programmable IC I know of was the Harris HM-01xx commercial diode matrix. These 14-pin DIP devices integrated an array of 40 or 48 silicon diodes, all connected by aluminum interconnects and fuses.
It took 750mA to blow one of the fuses. The figure below is a schematic of one of the diode arrays.
Harris began selling these diode arrays in the mid-1960s. Here is what people said about these arrays, as dictated by Napoleone Cavlan at the Computer History Museum, which includes discussions with Cavlan and Ronald Cline, who both worked at Signetics during the development of the first FPLA, the Signetics 82S100:
"I had some success in 1967 using another element. I believe these were diode matrices combined with fusible nickel-based chains made by Harris, with about 50 diodes per package arranged in rows and columns. I used these to design a magnetic core memory emulator for the ROM as a backup for the memory on the Poseidon guided missile. I also designed a programmer to program these chips."
In this series of articles,
I will discuss the oral history of the Signetics 82S100 FPLA development as told by Cavlan and Cline.
Cavlan's account of the Harris diode array shows that integrated fusible links, a key chip element required to create early programmable logic chips, existed as early as the 1960s.
After learning about these Harris diode arrays in the Cavlan oral history, I looked up the corresponding datasheet. When I first saw these diode arrays in the datasheet, I wondered what applications they might be used for. Suddenly, I felt a connection suddenly emerge that took me to a story I wrote ten years ago, the story of Stanley Frankel, an early computer pioneer who was almost lost in the mists of time when I began researching him. It took me three years to dig up enough information about Frankel to tell his story.
Frankel fell in love with computing and became an expert in using it to simulate physical processes while working for Robert Oppenheimer's Manhattan Project at Los Alamos, New Mexico, during World War II. He had been a graduate student of Oppenheimer's, who brought him to Los Alamos to help develop the atomic bomb.
Initially, he invented a method of distributing parts of large physics calculations to "computers" while running atomic bomb simulations on Marchant and Friedan electronic calculators, which Frankel did not know were operated by women at the time. He was developing prototypes for using computer algorithms to solve large problems, and later Frankel transferred these algorithms to the new IBM tabulating card readers purchased by Los Alamos to help with calculations.
Eventually, Frankel was connected to ENIAC, the world's first all-electronic programmable digital computer. Just as the war was coming to an end, Frankel's last assignment in the Manhattan Project was to run a simplified one-dimensional simulation of a deuterium-tritium fusion reaction to verify Edward Teller's hypothetical theory of the sequence of reactions inside a hydrogen bomb explosion. Frankel's simulation was the first real program to run on ENIAC, whereas before, programs were just test suites created by computer developers to find bugs in the machine.
Frankel's thermonuclear simulation project required one million punched Hollerith cards, which contained nothing but data. The cards were transported by train from New Mexico to Moore School in Pennsylvania, where ENIAC was located. ENIAC was not a stored-program computer; you had to physically program it, a bit like an FPGA, using wires to interconnect the various functional units to create the desired sequence of operations. While the results of this particular ENIAC calculation remain secret to this day, we do know that Los Alamos continued to develop Teller's hydrogen bomb after Frankel returned with his results.
By 1950, Frankel—the man who had successfully developed the first simulation algorithm for the creation of nuclear and thermonuclear weapons for the U.S. Department of Defense—had lost his security clearance due to Joe McCarthy, HUAC, and the Red Scare. Why? What crime or treachery had Frankel committed? It turned out that his father had been a communist in the 1930s, which disqualified him from further work on secret defense projects.
Needing to do unclassified work, Frankel began consulting with colleague Eldred Nelson and later joined the new digital computing group at the Caltech engineering department in Pasadena, California. This was the only way he could continue to work with computers at the time, since all computers were essentially mainframes.
While at Caltech, he managed to design a computer with very few active components. He succeeded in designing a computer that used only 113 vacuum tubes and a magnetic drum for storage. This computer used 1,450 germanium diodes to implement most of the digital logic, including the instruction decoder. Frankel described the design in his paper: "The logic design is implemented by a logic network consisting mainly of resistors and crystal diodes."
Frankel called his 113-tube computer "MINAC," sort of like "mini ENIAC." He designed the computer in 1954, and by 1956, MINAC was a commercially available computer. Librascope licensed the MINAC design from Frankel and used it to produce the desk-sized Librascope LGP-30 computer. Considered by some to be the first "personal" computer, the LGP-30 was not time-sharing, did not require a special air-conditioned room, and was powered by standard 115V wall current. In addition to its widespread use as a general-purpose computer for data processing, the LGP-30 was also used as an embedded computer for industrial testing and process control.
The diodes used in the MINAC design came from a component scrap bucket at nearby Hughes Semiconductor. That company had just started making germanium diodes, and Hughes encouraged Frankel to take as many as he wanted from the scrap pile, as they didn't meet specs but worked just fine in logic circuits. A decade later, Harris began making 40- and 48-diode arrays with field-programmable fuses and selling them to digital designers.
Yes, that's right. Before digital ICs, we used to use only discrete diodes and resistors to implement logic gates. It was called diode logic (DL) or diode resistor logic (DRL). Frankel reused this idea when he designed a desktop calculator for SCM in the mid-1960s - using lots of cheap, off-spec diodes to implement logic functions. This calculator, called the "Cogito 240", indirectly led to HP's entry into the calculator market. (But that's another story for another time.)
When I saw the data sheet and device schematic for the Harris diode array, I was immediately reminded of the 1450 germanium diodes that Frankel used in the MINAC design. These diode arrays were clearly programmable devices, and they could be used to build logic circuits, but they were not yet programmable logic devices.
The diode array data sheet in the 1984 Harris Bipolar catalog proudly declared that the arrays were "CMOS compatible." I have no idea what that means, but that's IC marketing for you. Perhaps it's because of the array's 20V reverse breakdown voltage. In theory, if you didn't mind risking electrocution, you could run some early CMOS logic families at supply voltages as high as 18 volts by inducing SCR latch-up inside the IC from a supply voltage spike and watching the device fail as it passed unlimited supply current. CMOS latch-up was a serious problem until the 1980s, but of course it no longer is. (Yes, that's another story for another time.)
In 1970, Harris announced the next evolutionary step in the history of programmable logic, the bipolar programmable read-only memory. The programmable element in these small PROMs was a fusible metal link made of nickel-chromium alloy instead of aluminum. Bipolar PROMs could certainly be used to create lookup tables for logic circuits, and they were well suited for developing small logic circuits and state machines, but the PROM sizes available at the time were 32×8 and 256×4 bits, which provided logic designers with very few input and output pins for implementing combinational logic from the PROM lookup tables.
Perhaps the greatest contribution of the bipolar PROM to the development of programmable logic was the development of manufacturing and testing methods to ensure that the fusible links on the PROM die were reliable. Harris added test rows and columns to his PROM design to allow destructive fuse testing during the wafer probing process. During wafer testing, one fuse was blown in each row and column of each device, which went a long way toward ensuring the overall functionality of the device.
By the mid-1970s, all the components needed to make field-programmable logic chips were in place; all that remained was for someone to put the components together and build the devices. This is the subject of the rest of this article.
Signetics creates the first successful programmable logic device: FPLA
The previous section discussed the earliest programmable ICs that could be used to implement logic circuits. Not exactly programmable logic, the Harris programmable diode array and PROM laid the foundation for later PLDs (programmable logic devices).
In this article, we tell the story of how Napoleone Cavlan, Ronald Cline, and Signetics developed the first commercially available FPLA (Field Programmable Logic Array). Both Cline and Cavlan had experience in memory IC design and both joined Signetics at the right time to take the next step in programmable logic. Cavlan was in charge of marketing and Cline was in charge of design engineering.
Engineers at the time were already accustomed to using PLAs for state machine design. For example, when I joined the R&D lab of the Computer Products Division of Hewlett-Packard in 1975, every design engineer in the lab had a copy of Chris Clare’s seminal book, Designing Logic Systems Using State Machines, and Clare was a project manager at the HP lab. Design, especially chip design based on Clare’s methodology, relied on MPLAs, which are discussed extensively in Chapter 5 of Clare’s book.
In 1973, National Semiconductor introduced the DM7575 MPLA with 14 inputs and 8 outputs, but this MPLA was not a great commercial success because it had a 90 nanosecond propagation delay and it also required going through an IC fab to add a final metal layer for characterization, which was again a slow and expensive process.
An on-chip MPLA is very useful when designing a custom IC, because you know a set of custom masks will be involved. But when you design a board, the need to design and manufacture mask programming parts can cause major headaches in the project schedule, so system designers are eager to use FPLA.
Although not a commercial success, National's DM7575 MPLA was significant because it laid the foundation for Signetics' FPLA 82S100, produced in 1975.
As Cavlan explains in his oral history:
“…National’s MPLA device came on line in 1975, but it didn’t take off because it used a mask process. Logic design is not a very structured process in general. In fact, if you say random logic, most of the time it really isn’t. That’s how I came up with the name – random logic. The inevitable variations don’t lend themselves well to MPLA, so the only use for the part is in more structured logic, like lookup tables, where you know more or less in advance what the organization is going to be and what the functionality is going to be. Despite this, MPLA didn’t take off.”
Cline described the ensuing events in a later oral history:
“The big steel companies knew what PLAs were at the time, and they used mask-programmable PLAs as microcode or microinstruction generators in their CPUs. But, as I told you before, we never considered this possibility. Also, after the success of 4K PROM, it was at this time that Napoleone came on the scene. I remember, I didn’t know anything at the time. No one told me.
“They didn’t want to distract me. But I found a request on my desk from an engineer at Honeywell, which was a large steel company at the time, ‘Can we make a fusible or fusible link PLA?’ That was the first time I had seen the concept, but I think the technical capability, the circuit capability, the application and knowledge, plus the inherent understanding of customer needs, all came together.”
Cavlan goes on to explain how the concept of the FPGA came about:
"The idea came from the success of mask-programming devices and the desire of people to modify logic in their design environment, and there seemed to be a lot of market traction for this type of device. So translating that idea into an architecture basically said, 'OK, there's a mask-programmed version available now. Let's make a version that's field programmable and can be used in a wide range of applications, not just bit-oriented but byte-oriented.'
In this regard, I have studied both areas and I am convinced that in designing a device with a set of programmable AND gates and programmable OR gates, whose I/O combinations are basically byte-organized (in our specific case, it is 16 inputs and 8 outputs) and have an output gate enable, it is not only suitable for generating bit-logic slices from the device..."
Using these concepts, Cline designed the first commercially successful FPLA, the Signetics 82S100, which could replace a small number of TTL chips, but had a propagation delay of 50 nanoseconds.
Cavlan describes the situation in detail in his oral history:
“Our first FPLA (82S100, PLS100) architecture was basically an AND-OR/NOR structure with a polarity inversion internally on the output, so you could do an AND-OR or AND-NOR function. But it had a very large input width that could take 16 variables at once and put them into any one of the gates. Not only that, but you could take a number of AND gates and distribute them to the outputs at will, and of course you could share them.
So when you look at logic functions that are done with TTL, often by manipulating all of those inputs, even for a single chip, you end up with multiple levels of TTL packaging. When you look at that chain, sometimes the delays are much larger than an FPLA, but sometimes the delays are smaller. It's a faster TTL chain, and in those cases, FPLA is not the best solution, but if speed is not critical, you can still put all of the TTL chips in one package into an FPLA, which is very useful.
The schematic for the Signetics 82S100 is shown below, with a fuse (not shown on the schematic) at each intersection of a horizontal row and vertical column.
The Signetics 82S100 sold well enough that it was even designed into Commodore personal computers, including the Commodore 64. (A programmed 82S100 FPLA that had been in the field for nearly 40 years now appears to be malfunctioning on a Commodore 64 computer. But the problem is so common that several replacement designs have been built using a 27C512 EPROM, a pair of PALs, or a Microchip/Atmel PLD on a daughterboard.)
However, the Signetics 82S100 was not the first FPLA. A month or two before this product was introduced, Intersil introduced the functionally similar IM5200 FPLA. Although the two FPLAs have the same product number (48), the 82S100 is about twice as fast as the IM5200 and has two additional input pins. It can be said that Intersil's FPLA was almost immediately eliminated. I am sure that Intersil was not very excited about this.
The success of the 82S100 FPLA was enough to encourage Signetics to expand the family with more PLDs based on the same technology. However, the flexibility of the fully programmable AND and OR arrays provided by the 82S100 design comes at a price. That is, its die is large, which makes the device relatively expensive and creates an opportunity for a less powerful, lower-priced alternative. That alternative is MMI's PAL family. It will appear in the near future.
Preparing for PALs
John Birkner grew up in a gold mine near Yosemite National Park in California. When he was six years old, his father contracted the "gold bug disease" (a reference to Edgar Allan Poe's novel "The Gold Bug", which can be understood as being affected by the gold rush), so the family moved here from Southern California to mine gold. Birkner was fascinated by electronics at an early age and became an engineer.
Eventually, Birkner began designing a series of small computers for Computer Automation in Irvine, California, called "Naked Minicomputers" or "Naked Minicomputers." It was at this time that he began to use TTL chips extensively and realized its limitations. It was also at this time that he became familiar with MMI, as he incorporated MMI's small bipolar PROMs into his CPU designs. At the time, these PROMs were a favorite of logic designers because they were fast and field programmable, which allowed for rapid changes to the design.
Signetics also tried to get Birkner to include the 82S100 FPLA in the minicomputer design, as the Signetics FPLA would have been a good fit. However, this was not accomplished for several basic engineering reasons. Birkner explained in the oral history:
"…I couldn't justify the cost and size of these big packages, and the propagation delays weren't fast enough. No, I didn't do it. But it made it more clear, 'Oh, maybe I should go over there and tell them what they need!'
And Birkner will soon have the opportunity to “tell them what they need.” In fact, he will also play a key role in ultimately driving the next evolutionary step in FPL development, which will be discussed in Part 3 of this series next week.
MMI's PALs open the door to programmable logic
Signetics salespeople tried to convince John Birkner, a minicomputer designer at Computer Automation Corporation in Irvine, California, to use the 82S100 in his designs, but Birkner thought the device was too costly, too large, and too slow, and he felt he should go to Silicon Valley to correct the IC supplier's mistakes.
John Birkner soon got the opportunity to "go there and tell them what they need." He felt the need to change jobs, so he rented a Janky Cessna 180 and flew from Irvine to San Jose, California. The plane was leaking oil throughout the flight, and Birkner had to land and refill the oil cooler several times. Finally, he barely made it to San Jose, where he interviewed with AMD and MMI. Both companies gave him offers, but Birkner ultimately chose MMI.
At the behest of Clive Ghester, MMI's boss, Birkner considered how to make FPLAs using the titanium-tungsten fuse technology that MMI used in PROMs. (MMI tried to become a second source for the Signetics 82S100 FPLA, but MMI's titanium-tungsten fuses did not work with the 82S100's mask-level design because the resistance of the titanium-tungsten fuses was much higher than the nickel-chromium fuses used by Signetics, and therefore could not be blown by the available programming voltages.)
In his oral history, Birkner explained his thought process following Ghester's request:
“…That’s when I started thinking, based on the 7400 TTLs I had memorized to solve problems on PC boards and the years of TTL design experience, how do we do Boolean minimization when you really can’t minimize?
“You just get these preconfigured chips that have four two-input NANDs, or two four-input ANDs, or some ORs. You need to use your brain to think about how to minimize the number of chips on the board when you really can’t minimize.
"One day it occurred to me that this "book" of 7400 TTL combinational and sequential circuits in my head could fit on a few chips, that is, all those AND gates and OR gates could fit into this PLA.
“Well, although I had the concept of how to design a PLA, I had never been tasked with, well, what would be a good product that a computer designer would use? Because I had been a computer designer before, I knew the needs of space, cost, and performance, and now I also knew about PROMs, knew the PROM architecture, and learned how to draw the architecture. I not only drew an architecture for a FPLA, but I drew all the little fuses, and used X’s to represent all the little connections, to look at both architectures… but the cost of doing so was too great, because the performance was so low.
"What if I flip this PROM over? I make the AND array an OR array, and the OR array an AND array, and the PROM becomes a hybrid of the two architectures, and I draw the new PAL architecture in the middle, and that combines the functionality they want. Not only can they see the PROM architecture, they can also see the FPLA architecture, which means they can see this new product.
“This new product is fast, cheap and small.”
Birkner realized that he could throw away some of the programmable features of the FPLA and combine all the AND terms into a programmable AND array with a fixed OR array, which would give him a chip that could do most of the FPLA's functions, but faster and cheaper. With additional work by the logic designer, the PAL could do almost everything the FPLA could do, but faster, with lower power, and at a lower cost, exactly the engineering tradeoffs that designers were eager to make. They felt smart when they successfully moved in the right direction along all three dimensions of the price/power/performance (PPP) curve.
The schematic for the MMI 16L8 PAL is shown below. Like the 82S100 FPLA (see Part 2 of this series), the PAL has a fuse at each row and column intersection, but this does not appear on the schematic, and any fuses that are not needed are blown during programming:
In March 1978, MMI placed a two-page advertisement in Electronic Design magazine introducing the first members of its new PAL series, which came in different input and output combinations, including with and without output registers or latches. As shown in the figure below, MMI packaged all of the devices in the initial PAL series in a 20-pin ultra-thin plastic DIP.
Image credit: Michael Holly
For all the reasons Birkner had thought of, PALs quickly became popular because they were fast enough to directly replace several layers of TTL gates, and power consumption was low enough that it would not be a problem. The cost, while not as low as MMI had thought, was low enough that design engineers would decide to use it after a little hesitation.
The biggest advantage PALS provides may not be reflected in the PPP engineering curve. It allows part of the design to be postponed to the later stage of the project to reduce design risks. When the requirements are unclear or the design is uncertain, the use of PAL can postpone the design decision of this part of the circuit until the circuit board is manufactured.
When the board is returned from the PCB shop and debugged, the engineer can change the design and fix the error in minutes by simply inserting a new PAL into the board. Of course, the successful use of this feature depends on the design engineer's ability to accurately predict where the design error may occur, and that is where you need to insert the PAL.
This "feature" may not seem like a big advantage today, as board designs can be sent to PCB manufacturers instantly via the Internet, and the manufactured boards can arrive as early as the next day, but in the late 1970s and early 1980s, board manufacturing took weeks, not just one or two days. Therefore, adding PAL to the design provided a few weeks of breathing room to finalize the design requirements suitable for PAL. Designers, including myself, took full advantage of this and came to rely on using PALS to add insurance against design risks.
Birkner was also heavily involved in marketing PALs. In his oral history, he specifically mentions the development of MMI's PAL manual, which was the primary marketing tool for PALs at the time. Here is how the manual describes MMI's PALs (Note: gender pronouns from that era have been intentionally left out. This is 1970s history! Folks! I'm retelling, not rewriting.)
PAL was an extension of the fusible link technology pioneered by Monolithic Memory for bipolar PROMs. This PROM first gave digital system designers the ability to "write on silicon" where designers could convert a blank PROM from a general purpose device to one containing a custom algorithm, microprogram, or Boolean transfer function in seconds. This opened up new areas for the use of PROMs in computer controlled storage, character generators, data storage tables, and many other applications. And today's multi-million dollar PROM market clearly demonstrates the applicability of this technology.
The key to the success of PROM is that it allows designers to quickly and easily customize chips to meet their unique requirements. PAL uses mature fuse technology to implement logic functions, extending this programmable flexibility. By using PAL circuits, designers can quickly and efficiently implement a variety of complex custom logic from logic gates to complex arithmetic functions.
PALs were so popular that they were the subject of Tracy Kidder's best-selling book, The Soul of the New Machine. Kidder's book describes the development of the Data General (DG) Eclipse MV/8000 minicomputer (code-named "Eagle") around 1978. The book was published in 1981 and won the Pulitzer Prize the following year. The Eclipse MV/8000 was DG's first 32-bit minicomputer, designed to compete with Digital Equipment Corp's VAX. Although the DG Eclipse MV/8000 was a 32-bit machine, it was compatible with the company's earlier 16-bit minicomputers, eliminating the need for separate 16-bit and 32-bit operating modes. This backward compatibility proved difficult to achieve, but it was very valuable to DG's existing customers.
Tom West managed the Eagle design team at DG and plays a central role in Kidder's book. Here is Kidder's description of Tom West's decision to use PALs:
In search of a technological edge, West thought that a circuit called a PAL was coming to chips. At the time, integrated circuit manufacturing was a pretty dangerous business. Factories could supposedly stop working for no apparent reason because of a small amount of dust, so conventional wisdom held that when building a new computer, you never wanted to use any brand-new chip unless at least two companies were making it. At the time, only one fairly small company was using PALs. But if PALs were really the way to go, then using them would win. So West decided to do just that.
Note that West was reluctant to use a single-source device, a design decision that engineers faced every day. Eventually, National Semiconductor, AMD, Raytheon, and Texas Instruments all became second or backup sources for MMI PALs. Even Signetics eventually caved and added PALs to its product line.
By the late 1970s, field programmable devices were booming. Starting in 1978, sales of MMI PALS doubled every year for six years. In 1982, four years after MMI introduced PALs to the engineering community, I began using their 16L8 PALs in circuit board designs for Cadnetix workstations. As was typical for system-level projects, parts of the workstation design were not fully defined by the time we needed to send the board design to the PCB shop, so I would place PALs in predicted locations where the design was uncertain, then develop the PAL configuration after the finished product came back. I frequently used PALs in memory management units to decode addresses and set page sizes, so I can say from personal experience that this PAL-centric design strategy worked very well at the time. (Things are different today, as we have better simulation tools.)
The PAL also proved very useful for the RAS and CAS signals required by early DRAMs. I used PALs for this application in the 1980s, as did my friend Ahmad Ghemmaghami, who designed and built a simple DRAM tester using an MMI PAL while working at Fujitsu in the 1980s. The 20-pin 16R8 PAL on this board, one of the original MMI PAL family members with registered outputs, is located to the right of the square white button in the upper left quadrant of the board and generates the RAS and CAS signal timing and refresh cycle required by the DRAM.
A photo of Ghemmaghami's single-board DRAM tester is below:
A PAL-based DRAM test board designed by Ahmad Ghemmaghami for Fujitsu to test 256Kbit and 1Mbit DRAM. It can perform "all 1", "all 0", checkerboard and reverse checkerboard memory tests.
Ghaemmaghami's board is an excellent example of mid-1980s logic design. It mixes a lot of cheap TTL MSI and SSI chips with one or a few PALs to use if the TTL design doesn't work for some reason. Note, however, that there is no microprocessor or microcontroller on this board, and 35 years later, you could probably replace all the chips on the board with a cheap microcontroller.
MMI's PALs are based on a variety of IC manufacturing and testing techniques that date back to Harris's field-programmable diode matrix, which opened the door to programmable logic for system designers in the 1960s. But these devices are not the final evolutionary step in field-programmable logic, which is still under development, and the next two steps on the evolutionary ladder, CPLDs (complex programmable logic devices) and FPGAs, will soon appear.
EPLD and CPLD are the next development direction of PLD
By the late 1970s, PALs had become the programmable logic device (PLD) of choice for system designers. It was a very successful product for MMI and became a target for other IC manufacturers who wanted to enter the PLD field, and in fact several companies did so.
The early 1980s was definitely the golden age of gate array development. Bob Hartmann founded Source III in 1980 to specialize in gate array design. The main gate array suppliers include LSI Logic, Signetics, Intersil, AMI and Fujitsu, who provide master chips and tools. The customer's task is to use the supplier's tools to create the design. Source III is an experienced middleman. This work prompted Hartmann and his consultant colleagues to consider the difficulty of developing gate arrays, NRE fees and time, and whether there is an available programmable logic device to replace these gate arrays under development.
In an oral history at the Computer History Museum with several founders and early Altera employees—Yiu-Fai Chan, Robert Frankovich, Robert Hartmann, Clive McCarthy, and Don Wong—
Hartmann described the thought process that led to the founding of Altera in 1983:
“After doing that for a few years, I saw the problems with that design system, including the cost of having to produce custom mask sets, or to make a specific part type. In a research book we wrote, we had this idea that wouldn’t it be great if someone could come up with something that could be programmed to do general logic after it was manufactured? We thought that would be a game changer. So after that, we said, ‘Why don’t we try to see if we can go in that direction?’ So we did.”
In Altera's first round of financing, Hartmann raised $750,000, which was not enough to design a chip, but enough to start the company. Venture capitalists wanted Altera to develop a test chip. Hartmann wanted to design a large design that could compete directly with the gate arrays on the market. Robert Frankovich met Hartmann while working at Fairchild in the 1970s and later co-founded Altera with Hartmann. He believed that Altera's first design should be a minimum viable product that could be sold, rather than a test chip, because a test chip would require the same effort as an actual product, but the result would only be a proof of concept and would not be a large PLD.
Frankovich won the debate by surveying the industry landscape in search of a “killer application” that would be an easy target for them to “grab a piece of the pie.” At the time, the most successful PLD family on the market was MMI’s 20-pin PAL family (discussed extensively in Part 3 of this series), so PAL was of course the primary target for Altera’s first PLD design.
Like other successful PLDs on the market in 1983, MMI's PALs used bipolar technology and metal fuse programming, resulting in the fastest devices. Altera wanted to take a different direction, and Frankovich knew that not everyone wanted fast devices, and he believed that bipolar technology would not scale to larger devices due to power consumption and heat dissipation issues. Altera's first PLD would compete with PALs, but future devices would need to compete with gate arrays and therefore would need to grow larger.
The Altera team chose the CMOS EPROM process as the technology for their first programmable logic device, which was very different from bipolar integrated circuits with metal fuse programming. This process technology also had several advantages: (1) it could be used in larger devices; (2) it was erasable; and (3) it had low power consumption.
The ability to produce larger devices would allow Altera to catch up to the market then served by gate arrays. Erasability meant that system designers like me wouldn't have a paper cup full of expensive, used PLDs on our benches to remind ourselves that design mistakes cost money. Of course, everyone liked low power. The only downside was the slower propagation delay, which meant that Altera's PLDs couldn't solve everyone's design problems. Of course, no IC could solve everyone's problems at the time.
Few chipmakers had CMOS EPROM manufacturing processes, and Japan's Ricoh was the only company willing to work with a small startup like Altera that had the process. As a result, Ricoh became Altera's first foundry, and Altera could claim to be the first true fabless chip design company.
But process technology was only the first challenge, the second challenge was packaging. EPROMs were packaged in wide dips with a quartz crystal, allowing UV light to enter the package and erase the EPROM battery. Because Altera wanted to compete with the 20-pin PAL, the company needed a 20-pin narrow package with a quartz crystal, but the technology didn't exist at the time, so Altera had to use it as a custom package.
Altera officially opened in June 1983 and produced its first chip in less than 6 months, launching the first programmable logic device EP300 before Christmas of that year. The EP300 development team consisted of 6 design engineers (Yiu-Fai Chan, Haugh suh, Robert Hartmann, Jim Sansbury, John Oh and Don Wong) and 4 layout designers (Bob Frankovich, Mark Belshaw, Susan Falk and Kathy Hopkins). This was possible at the time. You could gather a group of engineers, start a company in an office building in Silicon Valley, design a chip, tape it out, and have masks manufactured half a year later. At that time, such things were relatively simple. In July 1984, Altera launched the EP300 EPLD (erasable programmable logic device).
At the time, MMI offered seven different versions of the 20-pin PAL, but a single Altera EP300 could replace all of the MMI 20-pin PAL product lines and more. You could program the same Altera EP300 to emulate any of the seven MMI 20-pin PALs because MMI designed its PALs in a modular, mix-and-match fashion using several different macrocells, some of which included 1-bit output registers and others did not. You could mix and match these macrocells in your EP300 design and create PAL configurations that MMI did not offer. And all configurations could use the same Altera EPLD.
If you're not so fast, the CMOS EP300 input-to-output propagation delay is 90 nanoseconds, and MMI's bipolar PALs are more than four times that fast.
It turned out that not everyone needed that much speed, and Altera soon began selling large quantities of EPLDs. MMI was ready for the market, and Altera hit the center of the target with the EP300. Altera was profitable within two years of its founding, and had the opportunity to build larger and larger devices to compete with gate arrays. The Altera EP300 device had about 300 gates of logic in eight macrocells.
The success of MMI with PALs in the market caught the attention of Altera, and also attracted another competitor, Lattice Semiconductor. In 1983, Lattice was founded in Hillsboro, Oregon, and his GAL (Generic Array Logic) 16V8 device also copied the MMI PAL device architecture. Like Altera, Lattice chose to use CMOS process technology to manufacture the PAL replacement. Unlike Altera, he chose to use the Electrically Erasable CMOS (E2CMOS) process, which provides a higher on-chip device density and allows the device to be electrically erased. This feature allows 100% testing of manufactured 16V8 devices before shipment. Lattice can load the packaged GALs with multiple test patterns and then completely erase them after final testing.
Lattice's GALs are significantly faster than Altera's EP300 EPLDs. With a 15-nanosecond propagation delay from input to output, they are also faster than MMI's bipolar PALs. (Lattice emphasizes this fact in its marketing literature and prominently lists its applications hotline, 1-800-FASTGAL, at the bottom of every other page in the Lattice Generic Array Logic Handbook.)
Because of the CMOS process technology, GALs consume less power than bipolar PALs. Like Altera's EP300 EPLD, a 20-pin Lattice GAL can emulate any MMI 20-pin PAL, thereby reducing the number of blank devices that OEM system suppliers need to keep in inventory, which gives GALs a low-cost advantage. With these advantages, Lattice's GALs quickly gained market share in the PAL field.
Less than a year after Altera’s EP300 EPLD hit the market, Lattice introduced the GAL 16V8 PLD in April 1985 and immediately began spreading FUD (fear, uncertainty, and doubt) about Altera’s approach.
Here’s what the 1986 Lattice Generic Array Logic Handbook says about an unnamed competing product based on ultraviolet erasable CMOS (UVCMOS) process technology:
Although UVCMOS solves many of the shortcomings of the bipolar approach, it also introduces its own shortcomings. Although it has low power consumption and erase capability, this comes at the cost of slower speed and cumbersome erase process.
FUD-based marketing was, is, and will likely always be a hallmark of programmable logic marketing. Lattice didn’t invent FUD, it has been a part of technology marketing for decades. Because it has been a key component of automotive marketing for decades before that.
Meanwhile, AMD became an alternative source for MMI PALs in late 1980 or early 1981 by licensing PAL patents. Being an alternative source was AMD's main business, and the agreement was for patent use. AMD designed its own PALs, using its own semiconductor technology and improving on MMI's parts. For example, instead of using titanium tungsten fuses like MMI had in its original PALs and PROMs, AMD used more reliable platinum silicide fuses, which improved programming yields. While customers could return MMI PALs that were not properly programmed to the factory, this process added cost and only angered MMI's customers. AMD's sales staff took advantage of the situation and would outsell MMI simply by highlighting this advantage.
This alternative source of PALs allowed AMD sales to talk to many PAL customers about their needs. Engineers would pull out their schematics and show AMD sales how they were using existing parts, while they would also talk about the shortcomings of PALs and the additional features they would like to have. This was a great and in-depth market research.
But this market research also revealed some shortcomings, one of which was the constant shortage of PAL inputs and outputs that engineers encountered in PAL-based designs. It seemed that the selected PAL (no matter which one was chosen) always had one or two input or output pins shorted, or one of the outputs required a register but the other did not. As a result of this grassroots market research, AMD was able to define and develop a larger and better PAL called the 22V10, which was still a bipolar part, but it had more input and output pins and integrated more output macrocells (10 instead of 8). The 22V10 was packaged in a larger 24-pin package to accommodate the additional input and output pins.
In June 1983, AMD introduced the 22V10, and it became an overnight success. It was still the familiar PAL, but it met a need that engineers were eager for. In July 1985, Altera developed and released the EP600 EPLD in response to AMD's 22V10. The Altera EP600 emulated the 22V10 PAL in the same way that the EP300 emulated the MMI 20-pin PAL. Altera said the craze would come again. (Lattice also developed the GAL 22V10.)
However, the EP600 was not Altera's second EPLD. Altera introduced its second EPLD, the EP1200, in October 1984. The EP1200 packed about 1,200 logic gates into 48 macrocells and was packaged in a 40-pin DIP. Larger PLCC and PGA packages allowed the same EP1200 chip to support more input and output pins. The EP1200 EPLD went far beyond either PAL and moved toward gate array territory, but with a field programmable device. Its gate capacity was much smaller than any gate array, but it proved that Altera was heading in the right direction. The photo below shows the Altera EP1200 EPLD mounted in a 40-pin DIP.
Image credit: Michael Holley
(Note: Altera's EP600, EP900, and EP1200 EPLDs were featured in the inaugural issue of Michael Slater's Microprocessor Report in September 1987, and were the standouts. But this honor is somewhat dubious, since Slater's specialty was collecting and discussing chip error rates, a skill he honed at Asilomar before founding Microprocessor Report. Thus, Slater's brief EPLD article, which appeared in the "Bugs and Quirks" section of the first issue of his newsletter, had this to say: "Altera's EP600, 900, and 1200 devices have an automatic standby mode that activates when all inputs have not changed for 100 ns, and is designed to save power when operating with slowly changing inputs. The drawback is that there is a chance that combinatorial outputs may glitch if dependent inputs change while the device is in standby mode. So unless the system is fully synchronous and can tolerate glitches on the EPLD outputs, it will be necessary to set the 'Turbo' mode to 'quickly' switch. ' bit to prevent the chip from going into standby mode." This is useful advice, but I get the impression that Altera doesn't like this kind of publicity, although I may be mistaken.)
Later, programmable logic vendors' salespeople stopped calling their large programmable logic devices "PLDs" and instead exaggerated them to "CPLDs," complex PLDs. CPLDs continued to mimic the original macrocell organization in MMI's PALs, except that they had more inputs and outputs and incorporated more macrocells. Logically, a CPLD was a group of PAL macrocells, placed on the same chip and all connected together.
If you were expecting Altera to be an FPGA vendor at the start of this article, you probably would have had to wait until Altera introduced its first FPGA, the Flex 8000, in 1992. Altera quickly replaced the Flex 8000 FPGA with the Flex 10K family, the first FPGA to integrate embedded RAM blocks. Altera's Flex 10K family was very successful, but this is not a CPLD story. Initially, Altera was very cautious about Xilinx's FPGA patents, referring to the Flex 8000 and Flex 10K devices as "LUT-based plds" rather than FPGAs. However, three decades later, this no longer seems to be a problem.
FPGAs have many advantages over PALs, other smaller PLDs, and CPLDs. I will discuss the history of the first FPGAs at the end of this article.
Programmable diode arrays, FPLAs, PALs, EPLDs, and CPLDs paved the way for FPGAs
As discussed earlier in this article, the earliest PLDs developed along an easily traceable genetic line, starting with Harris Semiconductor programmable diode arrays in the 1960s, moving through bipolar PLMs, the Signetics 82S100 FPLA, MMI's PALs, and finally the PAL devices that went beyond CMOS by Altera and Lattice. In contrast, FPGAs (called "logic cell arrays" in the first press releases) came from a similar concept, field programmable logic, but in a completely different direction.
In the early 1980s, an engineer named Ross Freeman, working at Zilog, conceived a new type of reprogrammable logic circuit: a chip that could meet the logic design needs of an ASIC customer, but with the ability to instantly transform the design. At the time, there were dozens or even hundreds of ASIC companies designing and manufacturing custom chips for thousands of customers. However, it took many months to design and manufacture an ASIC, and Freeman's idea was that a custom IC could be developed and implemented in less than a day.
Freeman received a bachelor's degree in physics from Michigan State University in 1969 and a master's degree from the University of Illinois in 1971. He worked in the Peace Corps, taught mathematics in Ghana for two years, and then joined Teletype Corporation, where he gained experience in PMOS design. It is understood that Freeman was one of the first Zilog engineers to join Federico Faggin and designed the Zilog Z80-SiO chip. At the age of 30, he was already the engineering director of the Zilog Components department.
While working at Zilog, Freeman conceived a new type of hardware programmable device, which was destined to become the world's first FPGA. He applied for several patents for the technology, but Zilog was not interested. So Freeman decided to set up his own semiconductor company to study the FPGA concept and persuaded Zilog colleague Jim Barnett to join. At the same time, the two of them also persuaded Bernie Vonderschmitt, an executive with extensive electronics and semiconductor experience working at Zilog, to serve as the CEO of the startup.
Vonderschmitt worked at RCA Corp for more than 30 years before joining Zilog. In 1953, he led the development of RCA color television and became vice president and general manager of the company's solid-state division, which developed COSMOS (RCA's trademark name for CMOS). Seiko executives visited RCA's solid-state division to seek a license for the COSMOS process technology to start its electronic watch business. Vonderschmitt licensed RCA's COSMOS process to Seiko Epson, and by 1973 the company began selling Seiko digital LCD watches based on CMOS chips manufactured by Seiko Epson.
While serving as head of RCA's solid-phase division, Vonderschmitt gained a clear understanding of the huge capital demands of semiconductor manufacturing, as process technology needed to be upgraded every few years to keep up with Moore's Law, and companies that failed to invest in fabs would quickly drop out of the game.
Because chip manufacturing was only a sideline for RCA, which was more inclined to produce consumer devices and broadcast equipment, Vonderschmitt had difficulty getting the funds needed from the parent company to scale up production of new IC process technologies. Based on his experience in RCA's solid-state division, Vonderschmitt believed that a dedicated semiconductor fab would be too costly and burdensome. He vowed, "If I were to start a semiconductor company, it would be fabless."
In February 1984, Vonderschmitt, Freeman, and Barnett formally founded Xilinx. Vonderschmitt planned to focus Xilinx on designing innovative programmable devices and partnering with other companies to enter the capital-intensive chip manufacturing field. With the help of Seiko Epson executive Saburo Kusama, with whom he had a decade-long friendship, he got Seiko Epson to produce Xilinx's FPGA.
In fact, the task of designing the first FPGA fell to an engineer recruited from Zilog, his name was Bill Carter. Freeman originally hired him for the Zilog Z8000 microprocessor project. Later, Carter soon followed Freeman to Xilinx to work on FPGA design. He had previous experience in bipolar and MOS IC design, but Seiko Epson's process technology was CMOS, so Xilinx FPGA would be his first CMOS chip design.
The first FPGA, like all subsequent FPGAs, was a very large chip, and Vonderschmitt often advised Carter to keep the design as simple as possible and not try anything “too advanced or too exotic.” Minimizing design risk was important to Vonderschmitt, because he realized that a small startup offering a chip that required unfamiliar design tools and was manufactured through a unique fabless business model could easily scare off customers.
Because price competition in the watch industry is very fierce, Seiko Epson's CMOS digital watch chips use very conservative design rules to maximize production and reduce costs. Digital watch chips usually run at a frequency of 32kHz, which is very slow. But Xilinx's first FPGA design will not be too conservative, nor too slow, striving to achieve a clock frequency of tens of megahertz.
The first FPGA architectures were largely based on modular CLBs (Configurable Logic Blocks) and I/O blocks repeated many times, and reusing the same modules greatly simplified FPGA design, which was essential given the small design teams and minimal design tools available for startup. This situation is strikingly similar to the founding of Intel in 1968, when Robert Noyce and Gordon Moore founded Intel to become a memory device company, because memory chip designs used the same memory cells over and over again, allowing relatively complex chips to be produced with minimal design cost.
Carter's completed FPGA design required approximately 85,000 transistors to implement its 64 configurable logic blocks and 58 I/O blocks, while the 16/32-bit Motorola 68000 microprocessor required fewer transistors. The die size of the FPGA was larger than almost any chip produced at the time, and certainly larger than any chip Seiko Epson had ever built.
The first Xilinx chip was taped out in late May 1985, and the design team didn’t have the first batch of chips until early July. Seiko Epson sent a box with 25 finished wafers. But the first ten chips out of the box failed to tap out, which was not a good start. The eleventh chip showed some signs of life, but exhibited very high current consumption, and the last fourteen chips also failed completely due to shorts between power and ground.
Carter's team found that aluminum whiskers covered all of the first batch of wafers, and poorly etched aluminum metallization layers shorted the power and ground rails. Fortunately, only some of the failed whiskers on the wafer were weak enough to blow like a fuse. (The first generation of FPGAs were not designed to be programmable fuse devices, but because of a defective manufacturing process, they became programmable fuse devices.) The testing team successfully evaporated the whiskers by injecting a large amount of current into the wafer. It was a risky gamble, but there was nothing to lose if it lost.
After clearing the short, Carter was finally able to record a simple configuration bitstream into the device, successfully programming an inverter into one of the CLBs. While Freeman and Vonderschmitt were still traveling in Japan, Carter called them to report that the "DONE line had gone high," meaning that Xilinx had successfully created the world's most expensive inverter. After this initial success, the design team began programming more different logic circuits into the FPGA.
On November 1, 1985, a press release announced the Xilinx XC2064, the world's first "Logic Cell Array." This was the original classification for FPGAs, but the device was destined to be called an FPGA. Here is a photo of the Xilinx XC2064, in a 40-pin DIP package:
Strategically, the press release did not position the Xilinx XC2064 as a PLD, but rather as a new type of ASIC, a wording that reflects Xilinx's positioning of high-end logic programmability. The press release also claimed: "Logic cell arrays offer all the advantages associated with other ASICs - reduced chip count, high performance, smaller system size, lower power consumption, and high reliability - without the time, cost, and risk penalties." The second page of the press release states that "Logic cell arrays use a gate array-like architecture."
Clearly, this press release further distanced the new Xilinx FPGAs from the existing PALs and PLDs of the time:
Thus, the device is comparable to smaller gate arrays and offers more complexity than programmable array logic-type (or "PAL-type") devices, which typically offer 150 to 300 equivalent gates. Thus, the XC2064 can replace smaller gate arrays; 15 to 75 SSI and MSI (small and medium scale integration) devices; or four or more currently available PAL-type devices.
Despite these advantages, FPGAs have been slow to gain popularity, unlike the rapid adoption of MMI's PALs in the late 1970s. The reason is that John Birkner and MMI were able to ensure that chip designers could easily incorporate PALs into their existing design methodologies: PALs were fast and simple to understand, which suited existing TTL-based design techniques well. Although a single PAL chip was slightly more expensive than a TTL chip, it was not much more expensive.
Xilinx FPGAs were completely different. Like ASICs, FPGAs were much more complex than PALs, and therefore more difficult to understand and use. And FPGA design tools were completely foreign to most design engineers, and just like ASIC design tools, no one knew how to use FPGAs at first. Plus, early FPGAs were slower than both TTL and PAL devices, and the XC2064 FPGA couldn't replace that much logic with 64 CLBs. Seiko Epson's continued efforts to produce huge CMOS chips meant that Xilinx's FPGAs had to be priced higher to be profitable.
Despite all the odds, FPGAs succeeded. Over the next two decades, more and more FPGA vendors entered the market, targeting and absorbing other digital functions commonly found on circuit boards, including SRAM, level translators, DSP engines, Ethernet and other high-speed serial transceivers, and entire microprocessors. Over time, FPGA products began to branch out into high-end, mid-range, and low-cost product lines. As FPGA choices became more diverse, engineers began to use FPGAs more and more. After nearly four decades of market development, FPGAs are now widely used.
In 2009, the IEEE listed the Xilinx XC2064 as one of the "25 Microchips That Rocked the World" and in 2017 inducted it into the Chip Hall of Fame.
Acknowledgements: We would like to thank Mr. Huang Letian and Ms. Liu Yang from University of Electronic Science and Technology of China for their help in translation and proofreading.
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