2nm opens "team battle" mode
Latest update time：2021-09-01 20:35
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The 3nm process will be put into trial production this year, and if nothing unexpected happens, there will be no problem in mass production in 2022. On this basis, the industry has paid more attention to the progress of the 2nm process, especially after TSMC announced a major breakthrough in the 2nm process in the second half of 2020, people are more looking forward to it.
At the same time, just recently, 19 EU member states signed a joint statement to cooperate to "strengthen Europe's ability to develop next-generation processors and semiconductors." This includes leading manufacturing technologies that are gradually moving towards 2nm process nodes. In addition, Japan is working with TSMC to build advanced IC packaging and testing plants. The Taiwan Semiconductor Research Center (TSRI) has begun working with the National Institute of Advanced Industrial Science and Technology (AIST) of Japan to develop new transistor structures. Japanese media pointed out that this will help manufacture 2nm and more advanced process chips, and they plan to apply the results of the cooperation to the next generation of advanced semiconductors after 2024. And 2024 is the mass production year of TSMC's 2nm process.
At present, there is still some time before the 2nm trial production, and all parties are actively preparing. Around the wafer factory TSMC, major semiconductor equipment suppliers, material process service providers, EDA tool manufacturers, and major customers have begun to shift more and more attention to 2nm.
Fab
At present, TSMC’s leading advantage over Samsung in 3nm and 2nm processes is obvious, especially for 2nm. There is no authoritative information from Samsung yet.
In 2019, TSMC took the lead in starting the research and development of 2nm process technology. The corresponding technology development center and chip production factory are mainly located in Hsinchu, Taiwan. At the same time, 4 super-large wafer fabs are planned, mainly for the research and development and production of 2nm and more advanced processes.
TSMC established a 2nm project R&D team in 2019 to find a feasible path for development. After considering multiple conditions such as cost, equipment compatibility, technology maturity and performance, it was decided to adopt the MBCFET architecture based on the Gate-all-around (GAA) process to solve the physical limit problem of current control leakage caused by process miniaturization of FinFET. MBCFET and FinFET have the same concept, the difference is that the gate of GAA wraps around the channel on all four sides, and the source and drain are no longer in contact with the substrate.
GAA also has different forms depending on the design. The four most popular technologies are nanowires, multi-bridged fins with plate-like structures, hexagonal nanowires, and nanorings. Like TSMC, Samsung's GAA technology is also Multi-Bridge Channel FET (MBCFET), which is a multi-bridged fin with plate-like structures. However, Samsung used GAA at the 3nm node, while TSMC's 3nm still uses the FinFET process.
According to TSMC's 2nm process indicators, the Metal Track (metal unit height) is maintained at 5x, the same as 3nm. At the same time, the Gate Pitch (transistor gate spacing) is reduced to 30nm, and the Metal Pitch (metal spacing) is reduced to 20nm, both of which are 23% smaller than 3nm.
According to the plan, TSMC is expected to enter the 2nm process trial production stage in mid-2023 and start mass production a year later. In September 2020, according to Taiwan media reports, TSMC's 2nm process has made a major breakthrough and its R&D progress is ahead of schedule. The industry is optimistic that its risk trial production yield will reach 90% in the second half of 2023.
At present, in addition to the construction of the wafer fab, TSMC's 2nm talent arrangement and cultivation work is also proceeding in an orderly manner. According to reports, the company has promoted 4 employees in the past few months. These measures are intended to allow these employees to devote more energy to the research and development of 2nm manufacturing processes. It is reported that Geoffrey Yeap is now the senior director of the 2nm process platform R&D department. This position did not exist before. It was important to create this position when the company began to focus on the 2nm process. TSMC has high academic requirements for managers. The two newly promoted deputy general managers both have doctoral degrees.
equipment
For chip manufacturing, a lot of equipment is needed, but for such a high-precision process as 2nm, EUV lithography is undoubtedly the most critical. Statistics show that TSMC will install more than 50 EUV lithography machines by the end of 2021.
Japanese experts have reasoned and analyzed the EUV equipment required for TSMC's advanced process: in terms of the number of EUV layers, 7nm+ has 5 layers, 5nm has 15 layers, 3nm has 32 layers, and 2nm will reach 45 layers. Therefore, by 2022, when 3nm is mass-produced and 2nm is ready for trial production, the number of new EUV lithography machines required is expected to be 57. In 2023, when the production scale of 3nm is expanded and 2nm begins risk production, the number of new EUV lithography machines required will reach 58. By 2024, mass production of 2nm will be started, and the production scale will be expanded in 2025. By then, the number of new EUV lithography machines required is expected to be 62.
Although EUV will also be used for DRAM (especially 1a technology node and below), logic chips using advanced processes are still the main demand side. The High-NA EUV lithography system will start at the 2nm process node, and its mass production time is estimated to be 2025-2026. It is reported that ASML will complete the verification of the first High-NA EUV lithography system in 2022 and plans to deliver it to customers in 2023, mainly TSMC.
Regarding EUV technology, TSMC said that it would reduce mask defects and process stacking errors of lithography machines and reduce overall costs. This year, it will focus on improving the quality and cost of extreme ultraviolet technology in 2nm and more advanced processes. Earlier, there were reports that TSMC was raising more funds to purchase more EUV lithography machines with more advanced processes from ASML, all in preparation for the new process.
For 2nm and more advanced process technologies, EUV lithography machines are becoming increasingly important, but the output of EUV equipment is still a major problem, and its energy consumption is also very high.
At an online event held not long ago, Luc Vandenhove, CEO and president of the European microelectronics research center IMEC, said that progress has been made in cooperation with ASML on more advanced lithography machines.
Luc Vandenhove said that IMEC's goal is to commercialize the next generation of high-resolution EUV lithography technology and high-NAEUV lithography technology. As previous lithography competitors have long since withdrawn from the market, ASML has mastered the world's major advanced lithography production capacity. In recent years, IMEC has been working with ASML to study new EUV lithography machines, with the goal of reducing the process scale to 1nm and below.
Currently, ASML has completed the basic design of the NXE:5000 series high-NAEUV exposure system. As for the commercialization of the equipment, it will take until at least 2022, and it will take until 2023 for TSMC and Samsung to get the equipment.
Not long ago, researchers from the Chinese Academy of Sciences announced that they had broken through the bottleneck of designing 2nm chips and successfully mastered the technology of designing 2nm chips. Although such a development process makes people happy, there are still many problems. Although we have made technical research breakthroughs in this area, production cannot be achieved without EUV equipment. This reflects the importance of EUV lithography machines from one side. It is precisely because of this that wafer fabs with advanced process capabilities around the world have focused their attention on ASML.
Materials and Process
For advanced process technologies like 2nm, the follow-up of interconnect technology is key. Traditionally, copper interconnects are generally used, but when it comes to 2nm, the corresponding resistance-capacitance (RC) delay problem is very prominent, so the industry is actively looking for alternatives to copper.
At present, new interconnect technologies for 2nm and more advanced processes mainly include: hybrid metallization or pre-filling, combining different metal nesting processes with new materials to achieve smaller interconnections and less delay; semi-metal nesting, using subtractive etching to achieve tiny interconnections; super vias, graphene interconnects and other technologies. These are all under development.
Take hybrid metallization, for example, which uses two different metals in the interconnect. This makes sense for 2nm, at least for one layer. Via resistance is lower and reliability is improved compared to dual metal nesting, while maintaining the low resistivity of copper in the interconnect.”
The industry has also been exploring the use of ruthenium materials as liners in interconnects. Ruthenium is known for improving copper wettability and filling gaps, but while ruthenium has excellent copper wettability, it also has other disadvantages, such as shorter electromigration lifetime, and cell process challenges such as chemical mechanical polishing. This has reduced the use of ruthenium liners in the industry.
Other new interconnect solutions will also emerge, but they may not be commercially available until 2nm mass production in 2023/2024. According to IMEC's roadmap, the industry can move from today's dual-metal nesting process to the next generation technology, called 2nm hybrid metallization. There will also be semi-metal nesting and other solutions.
TSMC's research on materials has also made mass production of 2nm and more advanced processes possible. It is reported that TSMC and National Chiao Tung University in Taiwan have jointly developed the world's thinnest ultra-thin two-dimensional semiconductor material insulator with a thickness of only 0.7 nanometers, which is expected to further develop 2nm or even 1nm transistor channels.
EDA Tools
The new process technology cannot be separated from the support of EDA tools, and 2nm is no exception. The two major EDA manufacturers in the industry have also already made corresponding arrangements.
Faced with such a high-precision process technology, Cadence and Synopsys created a new EDA tool stack and developed a new IP library. The 2nm process requires chip developers to adopt new design rules and processes and remake everything they may have used before. Just like the shift to FinFET structure in 2014-2015, which increased chip design costs, the adoption of GAAFET may increase design costs again.
Synopsys said that the Liberty Technical Advisory Board (LTAB) and the Interconnect Modeling Technical Advisory Board (IMTAB) approved new modeling structures to address timing and parasitic parameter extraction issues for process nodes as low as 2nm. The ultra-low power requirements of mobile devices and various manufacturing challenges require new methods to ensure the best accuracy at signoff while supporting design tools to optimize for the lowest power consumption. In addition, the device architecture, mask, and imaging technology at these nodes force artifacts to be modeled through new extensions in the interconnect process file (ITF).
Synopsys has also launched the DTCO design methodology to integrate various advanced processes. It is reported that DTCO has helped customers achieve 2nm process design.
client
Not long ago, TSMC President Wei Zhejia said that with each generation of TSMC's process advancement, the speed and performance of customers' products can be improved by 30%-40% and power consumption can be reduced by 20%-30%. This may be the key to the company's continuous pursuit of advanced processes.
At present, there is no doubt that TSMC will be the first in the industry to mass-produce 2nm process chips. As its top customer in recent years, it is reasonable for Apple to be the first manufacturer to try out 2nm chips. In addition, after 2024, Qualcomm, Nvidia, AMD, etc. will become its 2nm technology customers.
At present, judging from TSMC's 2nm research and development progress, there is no problem in formal mass production in 2024. There are also reports that TSMC is already researching the 2024 2nm iPhone processor and has begun researching 1nm process node technology.
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
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