The three semiconductor giants start the competition for advanced process

Latest update time：2021-09-03 02:08

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Source: Content from " China Business Times ", thank you.

The demand for high-efficiency computing such as 5G, AI, and cloud computing continues to increase, driving the development of advanced semiconductor processes. As the difficulty of semiconductor miniaturization technology and the cost of R&D continue to increase, advanced semiconductor processes have gradually become a technology monopolized by a few IC manufacturers, which has also driven TSMC, Samsung, Intel and other companies to compete in advanced processes in recent years.

Over the past 50 years, IC manufacturers have mainly followed Moore's Law, which means that the number of transistors of a fixed area doubles every two years, continuously promoting the miniaturization of semiconductor processes. The most important key technology is the miniaturization technology that defines the feature size of transistors. With the continuous promotion of process miniaturization, the lithography technology nodes representing the size of transistors have continued to shrink, from the micron level in the 1980s to the nanometer level after 2004, and even to the 5-nanometer level that TSMC and Samsung introduced into mass production in 2020.

The advancement of miniaturization technology nodes mainly follows the International Technology Roadmap for Semiconductors (ITRS) jointly formulated by major global IC manufacturing associations. After entering the 90-nanometer node in 2004, facing the technical challenges and cost pressures of continued miniaturization, ITRS members, that is, major IC manufacturers, gradually withdrew from advanced process research and development, from 19 in 2001 to five in 2016: TSMC, Intel, Samsung, GlobalFoundries and UMC. China's SMIC followed closely behind, establishing the semiconductor professional foundry industry ecosystem, and chip specifications were no longer dominated by IC manufacturers, but were jointly determined by system requirements, IC design companies and IC manufacturers.

ITRS also retired in 2017, and was replaced by the International Component and System Roadmap (IRDS), which focuses more on new system requirements. As UMC and GlobalFoundries announced in 2017 and 2018 that they would abandon the research and development of processes below 7 nanometers, the world's advanced semiconductor processes finally focused on three major manufacturers: TSMC, Intel and Samsung.

In the development of advanced process technology, Intel was in an absolute leading position in the early years, with technology surpassing TSMC and Samsung by one generation. However, after entering the 14nm process in 2014, Intel encountered a bottleneck in the research and development of the next generation 10nm technology node, while TSMC and Samsung took advantage of the opportunity to catch up, respectively introducing the 7nm mass production process in 2018 and the 5nm mass production process in 2020.

Although Intel introduced the 10nm mass production process in 2019, it is about a year behind TSMC and Samsung, which has affected the production capacity and competitiveness of its own high-end chips. In order to curb the decline in market share of high-end chips, Intel has to carefully evaluate the plan of entrusting TSMC or Samsung to complete part of the chip production while actively investing in the research and development of the next technology node.

In terms of transistor structure selection, TSMC, Intel, and Samsung currently use the fin field effect transistor (FinFET) structure, and the next generation of transistor structure is the so-called gate-all-around (GAA) structure, which improves the control over the transistor's conductive channel through a larger gate contact area, thereby reducing operating voltage, reducing leakage current, and effectively reducing chip computing power consumption and operating temperature.

TSMC, which leads the technology, plans to continue using the FinFET structure at the 3nm node and plans to introduce the GAA structure at the 2nm node. However, Samsung and Intel, which lag behind, have chosen to introduce the GAA structure at the next technology node (Samsung at 3nm and Intel at 5nm), trying to use the advantages of the GAA structure to improve chip performance to cope with the competition with TSMC. Samsung is even planning to introduce the 3nm GAA mass production process in 2021, once again taking the lead in the breakthrough schedule of technology nodes.

In order to achieve continuous improvement in chip computing performance, Moore's Law requires that the number of transistors in a fixed area double every two years. However, with the advancement of technology nodes, the challenges and R&D costs of lithography technology and the accompanying thin film and etching technologies continue to rise. Moore's Law, which has lasted for more than 50 years, has reached its limit. Taking TSMC and Samsung as examples, the size reduction of each technology node can no longer achieve the goal of doubling the number of transistors, and new methods must be used to increase the density of transistors.

According to IRDS's plan, after 2021-2022, the FinFET structure will be replaced by the GAA structure, and the semiconductor advanced process will enter the 2-nanometer technology node. However, after that, the difficulty and cost of process miniaturization will be unbearable, and new transistor structures will be developed in the same technology node instead. The mainstream technology development direction is to increase the number and density of transistors by stacking transistors upward. The next step is to adjust the metal interconnect structure above the transistor, compress the interconnect space to form a denser circuit staggered stack, so as to reduce the overall area of the logic unit. It is expected that in the next 10 years, transistor and interconnect stacking technology will be the main direction of semiconductor process research and development, requiring close cooperation of all related technologies such as IC design, process, materials, packaging and process equipment.

Moore's Law is facing its limits. Silicon transistors, mainly metal oxide semiconductor field effect transistors (MOSFETs), have faced dual bottlenecks of technology and cost after the 2-nanometer technology node. New chip structures such as 3D stacking design of transistors and internal connections have been established as the development focus for the next decade.

In the face of the demand for improved chip computing performance, IC manufacturers must continue to invest in research and development. In addition to the improvement of existing process technology, the development of new structures, new materials or new component physics will be the new focus of competition.

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