Useful Tips | 20 common circuit interview questions, see how many you can answer correctly?

Latest update time：2020-07-03

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Q: What is the difference between synchronous circuits and asynchronous circuits?

Synchronous circuit: The clock input terminals of all flip-flops in the storage circuit are connected to the same clock pulse source, so the state changes of all flip-flops are synchronized with the applied clock pulse signal.

Asynchronous circuit: The circuit does not have a unified clock. The clock input of some triggers is connected to the clock pulse source, so that the state changes of these triggers are synchronized with the clock pulse, while the state changes of other triggers are not synchronized with the clock pulse.

Q: What is "wired-AND" logic? What specific hardware requirements are required to implement it?

The output terminals of two gate circuits are connected in parallel to realize the function of AND logic, which is called wired AND. In hardware, OC gates are used to achieve this, and a pull-up resistor is added to the output port. Not using OC gates may cause excessive current injection and burn out the logic gate.

Q: Explain setup and hold time violation, draw a diagram to illustrate, and explain the solution?

Setup/hold time is the time requirement between the input signal and the clock signal of the test chip. Setup time refers to the time when the data is stable and unchanged before the rising edge of the trigger clock signal arrives.

The input signal should arrive at the chip T time in advance of the rising edge of the clock (if the rising edge is valid). This T is the setup time. If the setup time is not met, the data cannot be entered into the trigger by this clock. Only on the next rising edge of the clock can the data be entered into the trigger.

The hold time refers to the time that the data remains stable after the rising edge of the trigger's clock signal arrives. If the hold time is not enough, the data cannot be entered into the trigger.

Setup time and hold time. Setup time refers to the time the data signal needs to remain unchanged before the clock edge.

Hold time refers to the time that the data signal needs to remain unchanged after the clock jump edge.

If the data signal lasts longer than the setup and hold time before and after the clock edge triggers, the excess amount is called the setup time margin and hold time margin, respectively.

Q: What is competition and risk-taking? How to identify it? How to eliminate it?

In combinational logic, contention occurs when the input signal of a gate has different arrival times due to different delays in its path.

The generation of burrs is called adventure. Judgment methods: algebraic method, graphical method (whether there are tangent Karnaugh circles), table method (truth table). If there are opposite signals in the Boolean expression, competition and adventure may occur.

Risks are divided into "1" risks and "0" risks. The solutions are: 1. Add Boolean elimination terms; 2. Add capacitors outside the chip; 3. Add a selection signal.

Q: Explain the three terms SRAM, SSRAM, and SDRAM?

SRAM: Static Random-Access Memory (SRAM) is a type of random access memory.

SSRAM: abbreviation of Synchronous Static Random Access Memory, which is synchronous static random access memory.

SDRAM: Synchronous dynamic random-access memory (SDRAM) is a dynamic random-access memory (DRAM) with a synchronous interface.

All accesses to SSRAM are initiated on the rising/falling edge of the clock. Address, data input and other control signals are all related to the clock signal. This is different from asynchronous SRAM, where access is independent of the clock, and data input and output are controlled by address changes. SDRAM: Synchronous DRAM synchronous dynamic random access memory.

Q: What are the concepts of FPGA and ASIC and what are their differences?

FPGA is a programmable ASIC.

ASIC, application-specific integrated circuit, is a circuit for a specific purpose, designed and manufactured specifically for a user. According to the specific requirements of a user, it can be supplied as a fully customized or semi-customized integrated circuit with low development cost and short delivery cycle.

Compared with other ASICs (Application Specific ICs) such as gate arrays, they have the advantages of short design and development cycle, low design and manufacturing cost, advanced development tools, no need for testing of standard products, stable quality and real-time online inspection.

Q: If the microcontroller does not run after power-on, what should I check first?

(1) First, confirm whether the power supply voltage is normal. Use a voltmeter to measure the voltage between the ground pin and the power pin to see if it is the power supply voltage, such as the commonly used 5V.

(2) The next step is to check whether the voltage on the reset pin is normal. Measure the voltage when the reset button is pressed and when the reset button is released to see if it is correct.

(3) Then check whether the crystal oscillator is oscillating. Generally, an oscilloscope is used to view the waveform of the crystal oscillator pin. After checking the above points, the fault can usually be eliminated.

If the system is unstable, it is sometimes caused by poor power supply filtering. Connecting a 0.1uF capacitor between the power pin and the ground pin of the microcontroller will improve the situation. If the power supply does not have a filter capacitor, you need to connect a larger filter capacitor, such as 220uF. When the system is unstable, you can try to connect a capacitor (the closer to the chip, the better).

Q: What is synchronous logic and asynchronous logic?

Synchronous logic is when there is a fixed causal relationship between clocks. Asynchronous logic is when there is no fixed causal relationship between clocks.

Q: What common logic levels do you know? Can TTL and COMS levels be directly interconnected?

Common logic levels: 12V, 5V, 3.3V.

TTL and CMOS cannot be directly interconnected, because TTL is between 0.3-3.6V, while CMOS is either 12V or 5V. CMOS output can be directly connected to TTL. TTL to CMOS requires a pull-up resistor to be added to the output port to connect to 5V or 12V.

Q: How to solve metastability?

Metastability refers to the inability of a trigger to reach a verifiable state within a specified period of time. When a trigger enters a metastable state, it is impossible to predict the output level of the unit, nor when the output will stabilize at a correct level.

During the metastable state, the flip-flop outputs some intermediate level, or may be in an oscillating state, and this useless output level can be cascaded down along the various flip-flops on the signal path.

The main solutions are:

Lower the system clock;
Use flip-flops (FF) and latches (LATCH) with faster response;
Introduce synchronization mechanism to prevent metastable state propagation;
Improve clock quality and use clock signals with fast edge changes;
Use devices with good process and large clock cycle margin.

Q: What are the differences between latches, triggers, and registers?

Trigger: The basic unit circuit that can store one bit of binary signal is collectively called a "trigger".

Latch: A single-bit flip-flop can only transmit or store one bit of data, but in actual work, it is often desired to transmit or store multiple bits of data at a time. To this end, the clock input terminals CP of multiple flip-flops can be connected and controlled by a common control signal, while each data port still receives data independently. The circuit that can transmit or store multiple bits of data at a time is called a "latch".

Register: In actual digital systems, a synchronous sequential logic circuit that can be used to store a set of binary codes is usually called a register. Since the flip-flop has a memory function, a register can be easily constructed using the flip-flop. Since a flip-flop can store one bit of binary code, connecting the clock ports of n flip-flops can form a register that stores n bits of binary code.

Difference: From the perspective of storing data, the functions of registers and latches are the same. The difference between them is that registers are controlled by synchronous clocks, while latches are controlled by potential signals.

It can be seen that registers and latches have different application scenarios, depending on the control method and the time relationship between the control signal and the data signal: if the data signal is valid and must lag behind the control signal, only latches can be used; if the data signal arrives ahead of the control signal and synchronous operation is required, registers can be used to store data.

Q: What is the difference between synchronous reset and asynchronous reset in IC design?

Asynchronous reset is not affected by the clock. When a chip system is initialized (or powered on), a global signal is needed to reset the entire chip to an initial state. Synchronous reset, on the other hand, requires the clock edge to reset the entire system.

Q: In multi-time domain design, how to handle signals crossing time domains?

Signal communication between different clock domains requires synchronization processing to prevent the metastable signal of the first-level trigger in the new clock domain from affecting the lower-level logic. For a single control signal, a two-level synchronizer can be used, such as level, edge detection and pulse. For multi-bit signals, FIFO, dual-port RAM, handshake signals, etc. can be used.

Signals that cross time domains must be synchronized by synchronizers to prevent metastable propagation. For example, if a signal in clock domain 1 is to be sent to clock domain 2, then before this signal is sent to clock domain 2, it must first be synchronized by the synchronizer of clock domain 2 before it can enter clock domain 2.

This synchronizer is a two-stage D flip-flop, whose clock is the clock of clock domain 2. This is done to prevent the signal in clock domain 1 from meeting the setup and hold time of the flip-flop in clock domain 2 and generating a metastable state, because there is no necessary relationship between them and they are asynchronous.

This can only prevent the propagation of metastable states, but cannot guarantee the correctness of the collected data. Therefore, usually only a few bits of signals are synchronized. For example, control signals or addresses. When the address is synchronized, the address should generally use Gray code, because Gray code only changes one bit at a time, which is equivalent to only one synchronizer working at a time, which can reduce the probability of error. For example, in the design of asynchronous FIFO, this method is used when comparing the size of the read and write addresses.

If a large amount of data is transmitted between two clock domains, an asynchronous FIFO can be used to solve the problem.

We can add a low-level enabled LockupLatch when crossing the ClockDomain to ensure that the Timing is correct.

Q: Given the setup and hold time of a reg, what is the delay range of the intermediate combinational logic?

The input signal should arrive at the chip T time ahead of the rising edge of the clock (if the rising edge is valid). This T is the setup time. If the setup time is not met, the data cannot be entered into the trigger by this clock. Only on the next rising edge of the clock can the data be entered into the trigger.

The hold time refers to the time that the data remains stable after the rising edge of the trigger clock signal arrives. If the hold time is not enough, the data cannot be entered into the trigger. That is, delay < period - Setup time - hold time

Q: The clock cycle is T, the maximum setup time of flip-flop D1 is T1max, and the minimum is T1min. The maximum delay of the combinational logic circuit is T2max, and the minimum is T2min. What conditions should the setup time T3 and hold time of flip-flop D2 meet?

The setup time refers to the time that the data is stable before the rising edge of the trigger's clock signal arrives. If the setup time is not enough, the data will not be entered into the trigger on this clock rising edge. The hold time refers to the time that the data is stable after the rising edge of the trigger's clock signal arrives. If the hold time is not enough, the data also cannot be entered into the trigger.

Tffpd: The response time of the trigger output, that is, how long it takes for the output of the trigger to change and stabilize after the rising edge of the clk clock arrives. It can also be understood as the output delay of the trigger.

Tcomb: The time required for the output of the trigger to pass through the combinational logic, which is the combinational logic delay in the title. Tsetup: Setup time Thold: Hold time Tclk: Clock cycle

Setup time tolerance: Equivalent to protection time, here the setup time tolerance is required to be greater than or equal to 0. Hold time tolerance: The hold time tolerance is also required to be greater than or equal to 0.

Q: What are the advantages and disadvantages of static and dynamic timing simulation?

Static timing analysis uses an exhaustive analysis method to extract all the timing paths in the entire circuit, calculate the propagation delay of the signal on these paths, check whether the setup and hold time of the signal meets the timing requirements, and find out the errors that violate the timing constraints by analyzing the maximum path delay and the minimum path delay.

It can exhaust all paths without input vectors, runs very fast and takes up less memory. It can not only perform comprehensive timing function checks on chip designs, but also use the results of timing analysis to optimize designs. Therefore, static timing analysis has been increasingly used in the verification of digital integrated circuit designs.

Dynamic timing simulation is a common simulation, because it is impossible to generate complete test vectors to cover every path in the gate-level netlist. Therefore, in dynamic timing analysis, it is impossible to expose the timing problems that may exist on some paths.

Q: What are the concepts and differences between LATCH and DFF?

(1) Concept

Level-sensitive storage devices are called latches; they are divided into high-level latches and low-level latches, which are used for synchronization between different clocks.

A bistable memory device composed of cross-coupled gates is called a trigger, which is divided into rising edge trigger and falling edge trigger. It can be considered as two latches with different level sensitivities connected in series. The first latch determines the setup time of the trigger, and the second latch determines the hold time of the trigger.

(2) Difference

The latch is level-triggered and asynchronously controlled. When the enable signal is valid, the latch is equivalent to a passage, and when the enable signal is invalid, the latch maintains the output state. The DFF is clock-edge-triggered and synchronously controlled.

Latches are prone to glitch, but DFF is not prone to glitch.

If gate circuits are used to build latches and DFFs, latches consume fewer gate resources than DFFs, which is where latches are superior to DFFs. Therefore, the integration of latches in ASICs is higher than that of DFFs, but it is just the opposite in FPGAs, because FPGAs do not have standard latch units, but have DFF units, and a latch requires multiple LEs to implement.

Latches greatly complicate static timing analysis.

The general design rule is: avoid latches in most designs. They will ruin your timing design, and they are very hidden, so only experienced people can detect them. The biggest harm of latches is that they cannot filter out glitches. This is extremely dangerous for the next level circuit. Therefore, latches should not be used wherever D flip-flops can be used.

In some places where there is no clock, latch can only be used. For example, if a clk is connected to the enable end of the latch (assuming it is a high level enable), the setup time required is the time required for the data before the falling edge of the clock, but if it is a DFF, then the setup time is the time required for the rising edge of the clock.

This means that if the data is later than the control signal, only latch can be used. This is the latch timing borrow mentioned above. Basically, it is equivalent to borrowing a high level time. In other words, the latch borrowing time is also limited.

Q: What is the difference between latch and register? Why register is used more now? How is latch generated in behavioral level description?

Latch is level triggered, Register is edge triggered, register operates under the same clock edge trigger, which conforms to the design concept of synchronous circuit, while latch belongs to asynchronous circuit design, which often makes timing analysis difficult, and inappropriate application of latch will waste a lot of chip resources.

Q: What is a phase-locked loop (PLL)? How does a phase-locked loop work?

A phase-locked loop is a feedback circuit that synchronizes the phase of the circuit clock with an external clock. PLL achieves synchronization by comparing the phase of the external signal with the phase of the voltage-controlled crystal oscillator (VCXO). During the comparison process, the phase-locked loop circuit will continuously adjust the clock phase of the local crystal oscillator according to the phase of the external signal until the phases of the two signals are synchronized.

In data acquisition systems, phase-locked loop is a very useful synchronization technology because it allows different data acquisition boards to share the same sampling clock.

Therefore, the phase of the local 80MHz and 20MHz time bases on all boards are synchronized, and thus the sampling clocks are also synchronized. Because the sampling clocks of each board are synchronized, data can be collected at exactly the same time.

Q: What are the types, advantages and disadvantages of basic amplifier circuits? Why is the differential structure widely used?

The basic amplifier circuit can be divided into common emitter amplifier circuit, common base amplifier circuit and common collector amplifier circuit according to their connection methods, which are referred to as common base, common emitter and common collector amplifier circuits for short.

The common emitter amplifier circuit can amplify both current and voltage. Its input resistance is in the middle among the three circuits, its output resistance is large, and its frequency band is narrow. It is often used as a unit circuit of a low-frequency voltage amplifier circuit.

The common base amplifier circuit can only amplify voltage but not current. It has a small input resistance, and its voltage amplification factor and output resistance are comparable to those of the common emitter amplifier circuit. Its frequency characteristics are the best among the three connection methods. It is often used in broadband amplifier circuits.

The common collector amplifier circuit can only amplify current but not voltage. It is the circuit with the largest input resistance and the smallest output resistance among the three connection methods, and has the characteristics of voltage following. It is often used in the input and output stages of voltage amplifier circuits, and also often adopts the emitter output form in power amplifier circuits.

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