Dry information | Detailed explanation of MOSFET structure and its working principle

Latest update time：2022-12-27 18:27

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1 Overview

The original meaning of MOSFET is: MOS (Metal Oxide Semiconductor), FET (Field Effect Transistor), that is, the gate of the metal layer (M) is separated from the oxide layer (O) by using the effect of the electric field to control the semiconductor. (S) field effect transistor.

Power field effect transistors are also divided into junction type and insulated gate type, but usually mainly refer to the MOS type (Metal Oxide Semiconductor FET) in the insulated gate type, referred to as power MOSFET (Power MOSFET). Junction power field effect transistors are generally called static induction transistors (Static Induction Transistor—SIT). Its characteristics are that the gate voltage is used to control the drain current, the driving circuit is simple, the driving power required is small, the switching speed is fast, the operating frequency is high, and the thermal stability is better than GTR, but its current capacity is small and the withstand voltage is low, generally only Suitable for power electronic devices with power not exceeding 10kW.

2. Structure and working principle of power MOSFET

Types of power MOSFET: According to the conductive channel, it can be divided into P channel and N channel. According to the gate voltage amplitude, it can be divided into: depletion type; when the gate voltage is zero, there is a conductive channel between the drain and the source, enhancement type; for N (P) channel devices, the gate voltage is greater than (less than) ) There is a conductive channel when zero, and the power MOSFET is mainly N-channel enhancement type.

2.1 Structure of power MOSFET

The internal structure and electrical symbols of the power MOSFET are shown in Figure 1; when it is turned on, only one polarity of carriers (multiple carriers) participates in conduction, and it is a unipolar transistor. The conductive mechanism is the same as that of low-power MOS tubes, but there are big differences in structure. Low-power MOS tubes are horizontal conductive devices. Most power MOSFETs adopt vertical conductive structures, also known as VMOSFETs (Vertical MOSFETs), which greatly improves the resistance of MOSFET devices. voltage and current capabilities.

According to the difference in vertical conductive structure, it is divided into VVMOSFET that uses V-shaped grooves to achieve vertical conduction and VDMOSFET with vertical conductive double-diffused MOS structure (Vertical Double-diffused MOSFET). This article mainly discusses VDMOS devices as an example.

Power MOSFET is a multi-integrated structure. For example, International Rectifier's HEXFET uses a hexagonal unit; Siemens' SIPMOSFET uses a square unit; Motorola's TMOS uses a rectangular unit. "Glyph arrangement.

2.2 Working principle of power MOSFET

Cutoff: Positive power is applied between the drain and source, and the voltage between the gate and source is zero. The PN junction J1 formed between the P base region and the N drift region is reverse biased, and no current flows between the drain and source.

Conductive: Apply a positive voltage UGS between the gate and source. The gate is insulated, so no gate current will flow. However, the positive voltage of the gate will push away the holes in the P region below it and attract the minority carriers-electrons in the P region to the surface of the P region below the gate.

When UGS is greater than UT (turn-on voltage or threshold voltage), the electron concentration on the surface of the P region under the gate will exceed the hole concentration, causing the P-type semiconductor to be inverted into N-type and become an inversion layer. This inversion layer forms an N channel. The PN junction J1 disappears, and the drain and source are conductive.

2.3 Basic characteristics of power MOSFET

2.3.1 Static characteristics; its transfer characteristics and output characteristics are shown in Figure 2.

The relationship between the drain current ID and the gate-source voltage UGS is called the transfer characteristic of the MOSFET. When ID is large, the relationship between ID and UGS is approximately linear, and the slope of the curve is defined as the transconductance Gfs.

The drain volt-ampere characteristics (output characteristics) of MOSFET: cut-off area (corresponding to the cut-off area of GTR); saturation area (corresponding to the amplification area of GTR); non-saturated area (corresponding to the saturation area of GTR). The power MOSFET works in a switching state, that is, it switches back and forth between the cut-off region and the non-saturated region. There is a parasitic diode between the drain and source of a power MOSFET, and the device turns on when a reverse voltage is applied between the drain and source. The on-state resistance of power MOSFETs has a positive temperature coefficient, which is beneficial to current sharing when devices are connected in parallel.

2.3.2 Dynamic characteristics; its test circuit and switching process waveform are shown in Figure 3.

Opening process; opening delay time td(on) - the time period from the up front moment to the moment when uGS=UT and iD starts to appear;

Rise time tr—the time period during which uGS rises from uT to the gate voltage UGSP when the MOSFET enters the unsaturated region;

The steady-state value of iD is determined by the drain supply voltage UE and the drain load resistance. The size of UGSP is related to the steady-state value of iD. After UGS reaches UGSP, it continues to increase under the action of up until it reaches steady state, but iD has not changed.

Opening time ton—the sum of opening delay time and rising time.

Turn-off delay time td(off) - the time period when up drops to zero, Cin discharges through Rs and RG, uGS drops to UGSP according to the exponential curve, and iD begins to decrease to zero.

Falling time tf—from when uGS continues to fall from UGSP, iD decreases until uGS

Turn-off time toff—the sum of turn-off delay time and fall time.

2.3.3 MOSFET switching speed.

The switching speed of MOSFET has a great relationship with the charge and discharge of Cin. Users cannot reduce Cin, but they can reduce the internal resistance Rs of the drive circuit, reduce the time constant, and speed up the switching speed. MOSFET only relies on multi-carrier conduction, and there is no minority carrier storage effect. Therefore The turn-off process is very fast, the switching time is between 10-100ns, and the operating frequency can reach more than 100kHz, which is the highest among major power electronic devices.

The field control device requires almost no input current when it is static. However, the input capacitor needs to be charged and discharged during the switching process, and a certain amount of driving power is still required. The higher the switching frequency, the greater the driving power required.

2.4 Improvement of dynamic performance

In addition to considering the voltage, current, and frequency of the device when applying it, it is also necessary to understand how to protect the device in the application so that the device is not damaged during transient changes. Of course, the thyristor is a combination of two bipolar transistors, and the large capacitance due to the large area makes its dv/dt capability relatively fragile. For di/dt, it also has a problem of expansion of the conduction area, so it also brings quite strict restrictions.

The situation of power MOSFET is very different. Its dv/dt and di/dt capabilities are often measured in nanoseconds (rather than microseconds). However, it also has dynamic performance limitations. We can understand these from the basic structure of power MOSFET.

Figure 4 is the structure of the power MOSFET and its corresponding equivalent circuit. In addition to the capacitance present in almost every part of the device, you must also consider that the MOSFET also has a diode in parallel. At the same time, from a certain angle, there is also a parasitic transistor. (Just like the IGBT also has a parasitic thyristor). These aspects are very important factors in studying the dynamic characteristics of MOSFET.

First of all, the intrinsic diode attached to the MOSFET structure has a certain avalanche capability. Usually expressed in terms of single avalanche ability and repeated avalanche ability. When the reverse di/dt is large, the diode will withstand a very fast pulse spike, and it may enter the avalanche zone. Once its avalanche capability is exceeded, the device may be damaged. As for any kind of PN junction diode, careful study of its dynamic characteristics is quite complicated. They are very different from our general understanding of the simple concept that a PN junction is conductive in the forward direction and blocked in the reverse direction. When the current drops rapidly, the diode loses its reverse blocking ability for a period of time, which is the so-called reverse recovery time. When the PN junction is required to be turned on quickly, it will not show very low resistance for a period of time. Once the diode has forward injection in a power MOSFET, the injected minority carriers will also increase the complexity of the MOSFET as a multi-sub device.

During the design process of power MOSFET, measures are taken to make the parasitic transistors in it as ineffective as possible. The measures are different in different generations of power MOSFETs, but the general principle is to make the lateral resistance RB under the drain as small as possible. Because only when sufficient current flows through the lateral resistance under the drain N region to establish a forward bias condition for this N region, the parasitic bipolar thyristor begins to have trouble. However, under severe dynamic conditions, the transverse current caused by dv/dt through the corresponding capacitance may be large enough. At this time, this parasitic bipolar transistor will activate, possibly causing damage to the MOSFET. Therefore, when considering transient performance, attention must be paid to each capacitance inside the power MOSFET device (which is the channel of dv/dt).

Transient conditions are closely related to line conditions, and sufficient attention should be paid to this aspect in applications. Only by having an in-depth understanding of the device can we understand and analyze the corresponding problems.

3. High-voltage MOSFET principle and performance analysis

Among power semiconductor devices, MOSFET plays an important role in various power conversions, especially high-frequency power conversions, with its high speed, low switching loss, and low driving loss. In the low-voltage field, MOSFET has no competitors, but as the withstand voltage of MOS increases, the on-resistance increases by 2.4-2.6 times. The growth rate forces MOSFET manufacturers and users to reduce the rated current by dozens of times to compromise the contradiction between the rated current, on-resistance and cost. Even so, the on-voltage drop caused by the on-resistance of high-voltage MOSFET at the rated junction temperature remains high. The on-voltage of MOSFETs with a withstand voltage of more than 500V under the conditions of rated junction temperature and rated current is very high, and the on-voltage of MOSFETs with a withstand voltage of more than 800V is surprisingly high. The conduction loss accounts for 2/3-4/5 of the total loss of MOSFET, which greatly limits its application.

3.1 Principles and methods of reducing on-resistance of high-voltage MOSFET

3.1.1 On-resistance distribution of MOSFETs with different withstand voltages.

MOSFETs with different withstand voltages have different resistance ratio distributions of each part of their on-resistance. For example, the epitaxial layer resistance of a MOSFET with a voltage of 30V is only 29% of the total on-resistance, and the epitaxial layer resistance of a MOSFET with a voltage of 600V is 96.5% of the total on-resistance. It can be inferred from this that the on-resistance of a MOSFET with a withstand voltage of 800V will be almost occupied by the epitaxial layer resistance. To obtain a high blocking voltage, a high resistivity epitaxial layer must be used and thickened. This is the fundamental reason for the high on-resistance caused by the conventional high-voltage MOSFET structure.

3.1.2 Ideas to reduce the on-resistance of high-voltage MOSFET.

Although increasing the die area can reduce the on-resistance, the increase in cost comes at a price that is not allowed for commercial products. Although the introduction of minority carrier conduction can reduce the conduction voltage drop, the price paid is the reduction of switching speed and the occurrence of tail current, the switching loss increases, and the high-speed advantage of MOSFET is lost.

The above two methods cannot reduce the on-resistance of high-voltage MOSFET. The remaining idea is how to separate the low-doping, high-resistivity region that blocks high voltage and the high-doping and low-resistivity of the conductive channel. For example, the low-doped high-voltage epitaxial layer can only increase the on-resistance during turn-on and has no other purpose. In this way, can the conductive channel be realized with high doping and low resistivity, and when the MOSFET is turned off, try to make this channel pinch off in some way, so that the voltage resistance of the entire device depends only on the low doping N-epitaxial layer. Based on this idea, in 1988 INFINEON launched COOLMOS with a built-in transverse electric field withstand voltage of 600V, making this idea a reality. The cross-sectional structure of a high-voltage MOSFET with built-in lateral electric field and the schematic diagram of high blocking voltage and low on-resistance are shown in Figure 5.

Different from the conventional MOSFET structure, the MOSFET with built-in lateral electric field is embedded in the vertical P region and sandwiched the N region of the vertical conductive region. When the MOSFET is turned off, a lateral electric field is established between the vertical P and N, and the N region of the vertical conductive region is The doping concentration is higher than that of the epitaxial region N-.

When VGS < VTH, the N-type conductive channel caused by the electric field inversion cannot be formed, and a positive voltage is applied between D and S, causing the internal PN junction of the MOSFET to be reverse-biased to form a depletion layer, and the vertically conductive N region will be exhausted. This depletion layer has a vertically high blocking voltage, as shown in Figure 5(b). At this time, the withstand voltage of the device depends on the withstand voltage of P and N-. Therefore, low doping and high resistivity of N- are required.

When CGS>VTH, the N-type conductive channel generated by the electric field inversion is formed. The electrons in the source region enter the depleted vertical N region through the conductive channel and neutralize the positive charges, thereby restoring the depleted N-type characteristics, so the conductive channel is formed. Since the vertical N region has lower resistivity, the on-resistance will be significantly lower than that of conventional MOSFETs.

Through the above analysis, we can see that blocking voltage and on-resistance are in different functional areas. Separating the functions of blocking voltage and on-resistance solves the contradiction between blocking voltage and on-resistance. At the same time, the surface PN junction during blocking is converted into a buried PN junction. At the same N-doping concentration, the resistance The breaking voltage can be further increased.

3.2 Main characteristics of built-in lateral electric field MOSFET

3.2.1 Reduction of on-resistance.

INFINEON's built-in transverse electric field MOSFET has a withstand voltage of 600V and 800V. Compared with conventional MOSFET devices, with the same die area, the on-resistance is reduced to 1/5 and 1/10 of conventional MOSFET respectively; the same rated current, The on-resistance dropped to 1/2 and about 1/3 respectively. Under the rated junction temperature and rated current conditions, the conduction voltage dropped from 12.6V and 19.1V to 6.07V and 7.5V respectively; the conduction loss dropped to 1/2 and 1/3 of conventional MOSFETs. Due to the reduction in conduction loss, heat generation is reduced and the device is relatively cool, so it is called COOLMOS.

3.2.2 Reduction in package size and thermal resistance.

The core of COOLMOS with the same rated current is reduced to 1/3 and 1/4 compared with conventional MOSFET, which reduces the package by two shell specifications.

Since the thickness of the COOLMOS die is only 1/3 of that of conventional MOSFET, the RTHJC of the TO-220 package is reduced from the conventional 1°C/W to 0.6°C/W; the rated power is increased from 125W to 208W, which improves the heat dissipation capacity of the die.

.2.3 Improvement of switching characteristics.

The gate charge and switching parameters of COOLMOS are better than those of conventional MOSFETs. Obviously, due to the reduction of QG, especially QGD, the switching time of COOLMOS is about 1/2 of that of conventional MOSFETs; the switching loss is reduced by about 50%. The decrease in off-time is also related to the low internal gate resistance of COOLMOS (<1Ω=.

3.2.4 Avalanche breakdown resistance and SCSOA.

At present, new MOSFETs are, without exception, resistant to avalanche breakdown. COOLMOS is also avalanche resistant. At the same rated current, the IAS of COOLMOS is the same as that of ID25℃. However, due to the reduction in die area, IAS is smaller than conventional MOSFET, and with the same die area, both IAS and EAS are larger than conventional MOSFET.

One of the biggest features of COOLMOS is that it has a short circuit safe operating area (SCSOA), while conventional MOS does not have this feature. The SCSOA of COOLMOS is obtained mainly due to changes in transfer characteristics and reduction in die thermal resistance. The transfer characteristics of COOLMOS are shown in Figure 6. It can be seen from Figure 6 that when VGS>8V, the drain current of COOLMOS no longer increases and is in a constant current state. Especially when the junction temperature increases, the constant current value decreases. At the highest junction temperature, it is about 2 times of ID25°C, that is, 3-3.5 times of the normal operating current. In the short-circuit state, the drain current will not rise to the intolerable ten times ID25℃ due to the gate's 15V driving voltage, so that the power dissipated by COOLMOS during short circuit is limited to 350V×2ID25℃, as much as possible Reduce tube core heating during short circuit. The reduced thermal resistance of the tube core allows the heat generated by the tube core to be quickly dissipated to the tube shell, inhibiting the rise rate of the tube core temperature. Therefore, COOLMOS can be driven at normal gate voltage, withstand 10μS short-circuit impact at 0.6VDSS power supply voltage, with a time interval greater than 1S, and can survive 1000 times without damage, so that COOLMOS can be effectively protected from short circuit like IGBT.

3.3 Current Development Status of High-Voltage MOSFET with Built-in Lateral Electric Field

Following the launch of COOLMOS by INFINEON in 1988, ST launched a 500V internal structure similar to COOLMOS in early 2000, allowing a 500V, 12A MOSFET to be packaged in a TO-220 tube case with an on-resistance of 0.35Ω, lower than the 0.4Ω of IRFP450, and a current Ratings are similar to IRFP450. IXYS also has MOSFETs using COOLMOS technology. IR Company has also launched SUPPER220 and SUPPER247 packaged super MOSFETs with rated currents of 35A and 59A respectively, on-resistances of 0.082Ω and 0.045Ω respectively, and on-state voltage drop of about 4.7V at 150°C. From the perspective of comprehensive indicators, these MOSFETs are better than conventional MOSFETs. It is not because the on-resistance decreases proportionally as the die area increases. Therefore, it can be considered that the above MOSFETs must have a special structure similar to the lateral electric field. It can be seen that It has become a reality to try to reduce the conduction voltage drop of high-voltage MOSFETs, and will definitely promote the application of high-voltage MOSFETs.

3.4 Comparison between COOLMOS and IGBT

The high-temperature conduction voltage drop of COOLMOS with 600V and 800V voltage resistance is about 6V and 7.5V respectively. The turn-off loss is reduced by 1/2, and the total loss is reduced by more than 1/2, making the total loss 40%-50% of conventional MOSFET. The conduction loss of conventional 600V withstand voltage MOSFET accounts for about 75% of the total loss. The balance point of ultra-high-speed IGBT corresponding to the same total loss reaches 160KHZ, of which switching loss accounts for about 75%. Since the total loss of COOLMOS is reduced to 40%-50% of conventional MOSFET, the corresponding IGBT loss balance frequency will be reduced from 160KHZ to about 40KHZ, increasing the application of MOSFET in high voltage.

From the above discussion, it can be seen that the new high-voltage MOSFET solves the problem of high conduction voltage drop that has long plagued high-voltage MOSFETs; it can simplify the overall machine design, such as the volume of the heat dissipation device can be reduced to about 40% of the original; the drive circuit and buffer circuit are simplified; it has Avalanche breakdown resistance and short circuit resistance; simplifying the protection circuit and improving the reliability of the entire machine.

4. Power MOSFET drive circuit

Power MOSFET is a voltage-type driving device, which has no storage effect of minority carriers and high input impedance. Therefore, the switching speed can be very high, the driving power is small, and the circuit is simple. However, the inter-electrode capacitance of the power MOSFET is relatively large. The relationship between the input capacitance CISS, output capacitance COSS, feedback capacitance CRSS and the inter-electrode capacitance can be expressed as:

The gate input terminal of the power MOSFET is equivalent to a capacitive network, and its operating speed is related to the internal impedance of the driving source. Due to the existence of CISS, the gate drive current is almost zero in static state, but a certain drive current is still required during the turn-on and turn-off dynamic processes. Assuming that the gate voltage required for saturated conduction of the switch is VGS, the turn-on time TON of the switch includes the turn-on delay time TD and the rise time TR.

During the turn-off process of the switch tube, CISS is discharged through ROFF, and COSS is charged by RL. When COSS is larger, VDS(T) rises slowly. As VDS(T) rises slowly, COSS rises rapidly as VDS(T) rises. When it decreases to close to zero, VDS(T) rises rapidly again.

According to the above analysis of the characteristics of power MOSFET, its driving usually requires: 1. The trigger pulse must have a sufficiently fast rise and fall speed; 2. The gate capacitance is charged with low resistance when turned on, and a low resistance discharge circuit is provided for the gate when turned off to increase the switching speed of the power MOSFET; 3. In order to reliably trigger the power MOSFET to turn on, the trigger pulse voltage should be higher than the turn-on voltage of the tube. In order to prevent mis-turning on, a negative gate-source voltage should be provided when it is cut off; 4. The driving current required when the power switch tube is turned on is the charging and discharging current of the gate capacitance. The larger the inter-electrode capacitance of the power tube, the larger the required current, that is, the greater the load capacity.

4.1 Introduction and analysis of several MOSFET drive circuits

4.1.1 Non-isolated complementary drive circuit.

Figure 7(a) shows a commonly used low-power drive circuit, which is simple, reliable and low-cost. Suitable for small power switching equipment that does not require isolation. The driving circuit shown in Figure 7(b) has fast switching speed and strong driving capability. In order to prevent the two MOSFET tubes from flowing through, a small resistor of 0.5~1Ω is usually connected in series for current limiting. This circuit is suitable for medium power applications that do not require isolation. Switchgear. These two circuits are characterized by simple structures.

Power MOSFET is a voltage-type control device, which will turn on as long as the voltage applied between the gate and source exceeds its threshold voltage. Due to the junction capacitance of MOSFET, a sudden rise in the voltage across its drain and source when turned off will generate interference voltage across the gate and source through the junction capacitance. The commonly used complementary drive circuit has a small turn-off loop impedance and a fast turn-off speed, but it cannot provide negative voltage, so its anti-interference performance is poor. In order to improve the anti-interference of the circuit, a first-level circuit composed of V1, V2, and R can be added on the basis of this driving circuit to generate a negative voltage. The circuit schematic is shown in Figure 8.

When V1 is turned on, V2 is turned off, the gate and source of the upper tube of the two MOSFETs are discharged, and the gate and source of the lower tube are charged, that is, the upper tube is turned off and the lower tube is turned on, then the driven power tube Turn off; on the contrary, when V1 turns off, V2 turns on, the upper tube turns on, and the lower tube turns off, causing the driven tube to turn on. Because the gate and source of the upper and lower tubes charge and discharge through different loops, including the loop of V2, since V2 will continue to exit saturation until it turns off, the turn-on of S1 is slower than the turn-off of S2. Turning on is faster than turning off, so the heat levels of the two tubes are not exactly the same. S1 heats up more than S2.

The disadvantage of this drive circuit is that it requires dual power supplies, and since the value of R cannot be too large, otherwise V1 will be deeply saturated and affect the turn-off speed, so there will be a certain loss on R.

4.1.2 Isolated drive circuit

(1) Forward drive circuit. The circuit principle is shown in Figure 9(a), N3 is the demagnetization winding, and S2 is the driven power tube. R2 is a damping resistor that prevents the gate and source terminal voltages of the power tube from oscillating. Since the leakage inductance is not required to be small, and considering the speed, R2 is generally small, so it is ignored in the analysis.

The equivalent circuit diagram is shown in Figure 9(b). The secondary side that is not required by the pulse is connected in parallel with a resistor R1. It is used as a dummy load of the forward converter to eliminate the oscillation of the output voltage during the turn-off period and cause false turn-on. At the same time, it can also be used as an energy discharge circuit when the power MOSFET is turned off. The conduction speed of the drive circuit is mainly related to the size of the equivalent input capacitance of the driven S2 gate and source, the speed of the drive signal of S1, and the size of the current that S1 can provide. It can be seen from simulation and analysis that the smaller the duty cycle D, the larger R1, and the larger L, the smaller the magnetizing current, the smaller the U1 value, and the slower the turn-off speed. This circuit has the following advantages:

①The circuit structure is simple and reliable, realizing isolated drive.

② Only a single power supply can provide positive voltage when turned on and negative voltage when turned off.

③When the duty cycle is fixed, through reasonable parameter design, this drive circuit also has a faster switching speed.

The shortcomings of this circuit are: first, because the secondary side of the isolation transformer requires a false load to prevent oscillation, the circuit loss is large; second, the turn-off speed changes greatly when the duty cycle changes. When the pulse width is narrow, the turn-off speed of the MOSFET gate becomes slower due to the reduction of stored energy.

(2) Complementary drive circuit with isolation transformer. As shown in Figure 10, V1 and V2 work complementary, the capacitor C plays the role of isolating DC, and T1 is a high-frequency, high-magnetic rate magnetic ring or magnetic tank.

The voltage on the isolation transformer is (1-D) Ui when it is turned on and D Ui when it is turned off. If the main power tube S reliably turns on voltage is 12V, and the primary and secondary turns ratio of the isolation transformer N1/N2 is 12/[ (1-D)Ui]. In order to ensure that the GS voltage is stable during the conduction period, the C value can be slightly larger. This circuit has the following advantages:

①The circuit structure is simple and reliable, and has electrical isolation function. When the pulse width changes, the driver's turn-off capability does not change.

② This circuit only needs one power supply, that is, it works with a single power supply. The function of the DC blocking capacitor C can provide a negative voltage when turning off the driven tube, thereby accelerating the turning off of the power tube and having a high anti-interference ability.

However, a major disadvantage of this circuit is that the amplitude of the output voltage changes as the duty cycle changes. When D is small, the negative voltage is small, the anti-interference performance of the circuit becomes poor, and the forward voltage is high. Care should be taken to ensure that the amplitude does not exceed the allowable voltage of the MOSFET gate. When D is greater than 0.5, the forward voltage of the driving voltage is less than its negative voltage. At this time, care should be taken to ensure that the negative voltage value does not exceed the MOAFET gate allowable voltage. Therefore, this circuit is more suitable for situations where the duty cycle is fixed or the duty cycle changes within a small range and the duty cycle is less than 0.5.

(3) Drive circuit composed of integrated chip UC3724/3725

The circuit configuration is shown in Figure 11. Among them, UC3724 is used to generate high-frequency carrier signals, and the carrier frequency is determined by the capacitor CT and resistor RT. Generally, the carrier frequency is less than 600kHz. High-frequency modulated waves are generated at both ends of pin 4 and pin 6. After being isolated by a high-frequency small magnetic ring transformer, they are sent to pins 7 and 8 of the UC3725 chip. After being modulated by UC3725, the drive signal is obtained. There is a waveform inside the UC3725. The special base rectifier bridge simultaneously rectifies the high-frequency modulated wave of pins 7 and 8 into a DC voltage to provide the power required for driving. Generally speaking, the higher the carrier frequency, the smaller the drive delay, but if it is too high, the anti-interference becomes worse; the larger the magnetizing inductance of the isolation transformer is, the smaller the magnetizing current is, and the UC3724 generates less heat, but if it is too high, the number of turns increases, which increases the influence of parasitic parameters. It will also reduce the anti-interference ability. According to the experimental data, it is concluded that for signals with a switching frequency less than 100kHz, a carrier frequency of (400~500kHz) is generally better. For the transformer, a higher magnetic permeability such as 5K, 7K and other high-frequency ring cores should be used, and the primary magnetizing inductance should be less than approximately About 1 millihenry is good. This kind of drive circuit is only suitable for occasions where the signal frequency is less than 100kHz. If the signal frequency is too high relative to the carrier frequency, the relative delay will be too much, and the required drive power will increase. The UC3724 and UC3725 chips will generate a higher temperature rise, so 100kHz The above switching frequency is only possible for MOSFETs with smaller capacitance. It is a good drive circuit for situations where the switching frequency is less than 100kHz around 1kVA. This circuit has the following characteristics: single power supply operation, isolation of control signal and driver, simple structure and small size, especially suitable for occasions where the duty cycle changes are uncertain or the signal frequency changes.