Cadence joins hands with TSMC to advance 7nm FinFET Plus design innovation

New 7nm FinFET Plus tool certification and 7nm process optimization

Cadence digital implementation and signoff tools are now fully certified for TSMC 7nmFinFET Plus and 7nm processes, and process design kits (PDKs) are now available for download. Digital implementation and signoff full-process tools include Innovus™ design implementation system, Quantus™QRC extraction solution, Tempus™ timing signoff solution, Voltus™ IC power integrity solution, and Voltus-Fi custom circuit power integrity solution , Physical Verification System (PVS) and Layout Dependent Effect (LDE) electrical analysis tools. Tool features designed specifically for the 7nm FinFET Plus process include EUV layer support and extended via-pillar support. Digital and signoff flow enhancements for the 7nm process, including trace congestion and IR-driven placement, optimized clock buffer clustering/placement/routing, and improvements to the NanoRoute™ tool engine to reduce runtime and improve the quality of design rule checks (DRC).

Custom/analog circuit simulation tool certifications for 7nm FinFETPlus and 7nm processes include Specter Accelerated Parallel Simulator (APS), Spectree Virtuoso circuit schematic editing tool, Virtuoso simulation design environment (ADE). The above tools provide advanced device capture and accelerate customized placement and routing processes to help customers improve productivity and meet power consumption, multiple exposure, density and electromigration (EM) requirements.

Design methodologies can be enhanced through the advanced capabilities of the Virtuoso advanced process node platform, allowing customers to achieve higher custom physical design throughput when using 7nm FinFET Plus and 7nm process technology compared to traditional unstructured design methodologies. Using advanced node capabilities including multiple exposure and color-aware layout, Module Generator (ModGen) device array, automated FinFET placement and differential analysis, early users can achieve similar cycle times to the 16nm process.

7nm FinFET Plus library model extraction tool flow delivery

In addition to tools already certified for TSMC’s 7nm FinFET Plus and 7nm process technologies, the Virtuoso Liberate™ parametric characterization solution and the Virtuoso Variety™ statistical parametric characterization solution have also been certified and will provide support for advanced timing, noise and power models including The 7nmFinFET Plus process within provides accurate Liberty content libraries. With innovative free variable form (LVF) models, the solution enables accurate sign-off of process changes, creation of electromigration (EM) models, and EM signal optimization and sign-off.

"Our close collaboration with TSMC on 7nm FinFET Plus and 7nm process technology allows us to provide the best solutions for customers using advanced process nodes," said Cadence Executive Vice President, Digital and Signoff Group, Systems and Verification Group said Dr. Anirudh Devgan, General Manager. "The latest certified EDA tools allow us to serve an increasing number of advanced process designs in the mobile and high-performance computing market segments. Customers can more easily adopt our technology and develop high-quality innovative designs."

"Customers of our advanced process nodes have successfully used 7nm process technology to design and wafer complex SoCs, and 7nm FinFET Plus process technology has also had many early customers." said Suk Lee, senior director of TSMC's design architecture marketing department. "Tool and process qualification through our strong collaboration with Cadence on the 7nm and 7nm FinFET Plus processes ensures that our customers can quickly achieve their design goals within a predictable project schedule."