Cadence HPC full range of solutions

A new generation of electronic systems will significantly impact our daily lives. From smart car applications and network connections to smart home security and protection, aerospace and defense, and even medical and other fields, everything related to our daily lives is connected. Their vast array of sensors operating at the edge generate vast amounts of data.

How do we transfer, process, analyze and store this data? Keep your data safe and secure at the same time?

The answer is to use High Performance Computing (HPC).

How to deal with the data explosion

• There is a need to increase higher computing density in CPUs targeted at data center servers.

• In terms of chip architecture, it is necessary to use multi-die interconnection to provide more external interfaces.

• Use chiplets and 2.5D/3D-IC packaging to solve yield problems caused by design sizes approaching or exceeding the mask size.

How to deal with higher storage needs

• DDR5/HBM2e memory processing

• PCIe Gen6/CXL2.0/UCIe high-speed interface

In response to the above challenges, Cadence provides solutions in all aspects of design, verification, and implementation to help customers optimize IP, chips, and systems suitable for ultra-large-scale applications. Providing industry-leading virtual cloud computing, fast verification engines and intelligent verification applications, allowing customers to find and fix more vulnerabilities in a short time at low cost. Solve the chip design challenges caused by the increasing complexity of SoC chip architecture.

▷ In response to the chip design challenges brought about by the increasing complexity of SoC chip architecture, Cadence Design IP provides high-performance, low-latency network infrastructure and storage solutions:

▷ In view of the reduced chip verification efficiency caused by the large scale of SoC design, Cadence provides faster simulation speed and larger design capacity:

▷ For SoC system-level performance analysis and software and hardware collaborative verification challenges, Cadence provides:

▷ For the low power consumption and thermal requirements of edge computing:

▷ For data center and IoT applications from edge to cloud:

▷ In response to the increase in computing density, the chip size exceeds the mask size:

Nvidia and Cadence collaborate to address the enormous challenges of ultra-large-scale SoC chip design and verification

As the inventor of the GPU and the leader in artificial intelligence computing, NVIDIA is one of the creators of the world's largest SoC chips. As the complexity of chips and systems increases, NVIDIA needs to use hardware simulation technology that keeps pace with the times to deal with chip, System and software challenges.

Cadence's Palladium Z2 and Protium X2 (System Power Dynamic Duo) enable NVIDIA to move designs from hardware emulation accelerators to FPGA-based systems. NVIDIA engineers can easily and calmly move from the Palladium hardware emulation acceleration platform to FPGA-based systems. Protium system.

NVIDIA engineers can now take a multi-billion-gate design, compile it, create a simulation model, and import it into a simulation accelerator in just four hours, whereas not long ago this same process would have been possible. What took 48 hours or even 72 hours now only takes 4 hours. This is a breakthrough technology in the field of hardware emulation technology.