How to use MCU SPI to access ADC with non-standard SPI interface

Can I use an MCU to access a non-standard SPI interface?

Yes, but it may require some extra effort.

Many current precision analog-to-digital converters (ADCs) have a serial peripheral interface (SPI) or some type of serial interface to communicate with controllers including microcontroller units (MCUs), DSPs, and FPGAs. The controller writes or reads the ADC internal registers and reads the conversion codes. SPI is becoming increasingly popular due to its simple printed circuit board (PCB) routing and faster clock rates than parallel interfaces. Furthermore, it is easy to connect an ADC to a controller using standard SPI.

Some new ADCs have SPI, but some ADCs have non-standard 3-wire or 4-wire SPI as slaves because they want to achieve faster throughput. For example, the AD7616, AD7606, and AD7606B families have two or four SDO lines, which provide faster throughput in serial mode. The AD7768, AD7779, and AD7134 families have multiple S DO lines and act as SPI masters. Users often encounter difficulties when designing microcontroller SPI to configure the ADC and read code.

Figure 1. The AD7768 is used as a serial master with two data output pins (14001-193).

SPI is a synchronous, full-duplex, master-slave interface. Data from the master or slave is synchronized on the rising or falling edge of the clock. The master and slave can transmit data at the same time. Figure 2 shows a typical 4-wire MCU SPI interface connection.

Figure 2. Standard MCU SPI connection to ADC slave.

To start SPI communication, the controller must send the clock signal and select the ADC by enabling the CS signal (usually an active low signal). SPI is a full-duplex interface, so the controller and ADC can output data simultaneously through the MOSI/DIN and MISO/DOUT lines respectively. The controller SPI interface allows the user to flexibly select the rising or falling edge of the clock to sample and/or shift data. For reliable communication between the master and slave, the user must comply with the digital interface timing specifications of the microcontroller and ADC chip.

Figure 3. Example of SPI data clock timing diagram.

If the microcontroller SPI and ADC serial interface have standard SPI timing mode, it is not a problem for users to design PCB layout and develop driver firmware. However, the serial interface port of some new ADCs is not a typical SPI timing mode. It seems impossible for MCU or DSP to read data through the AD7768 serial port (a non-standard timing SPI port), as shown in Figure 4.

Figure 4. AD7768 FORMATx = 1× timing diagram, output only through DOUT0.

This article will describe methods for manipulating the standard microcontroller SPI to interface with an ADC that has a nonstandard SPI port.

This article will give four solutions for reading ADC codes through a serial interface:

• Solution 1: MCU as SPI slave, interfacing with ADC as SPI master through one DOUT line.

• Solution 2: MCU as SPI slave, interfacing with ADC as SPI master through two DOUT lines.

• Solution 3: MCU as SPI slave, interfacing with ADC as SPI master via DMA.

• Solution 4: MCU acts as SPI master and SPI slave and reads data through two DOUT lines.

As shown in Figure 4, when FORMATx = 11 or 10, Channel 0 to Channel 7 output data only through DOUT0. In standard operating mode, the AD7768 /AD7768-4 works as a master and data flows into an MCU, DSP, or FPGA. The AD7768/AD7768-4 provides data , a data clock (DCLK), and a falling edge frame enable signal (DRDY) to the slave.

The STM32Fxxx series of microcontrollers are widely used in many different applications. The MCU has multiple SPI ports that can be configured as an SPI master or slave using typical SPI timing modes. The method described below can also be applied to other microcontrollers with 8-bit, 16-bit or 32-bit frames.

The AD7768/AD7768-4 are 8-channel and 4-channel simultaneous sampling ∑-∆ ADCs, respectively. Each channel has a ∑-∆ modulator and digital filter to support simultaneous sampling of AC and DC signals. These devices achieve 108dB dynamic range at a maximum input bandwidth of 110.8kHz, with typical performance of ±2ppm INL, ±50µV offset error, and ±30ppm gain error. AD7768/AD7768-4 users can trade off between input bandwidth, output data rate, and power consumption, and select one of three power modes to optimize noise targets and power consumption. The flexibility of the AD7768/AD7768-4 makes it a reusable platform for low power DC and high performance AC measurement modules. Unfortunately, the serial interface of the AD7768 is not a typical SPI timing mode, and the AD7768 acts as a serial interface host. Generally speaking, users must use an FPGA/CPLD as their controller,

For example, use the 32F429IDISCOVERY and AD7768 evaluation board. The connection of the workaround SPI line is shown in Figure 5. In this setting, all eight channels of data of the AD7768 are output through DOUT0 only.

Figure 5. The AD7768 outputs data through DOUT0 to the STM32F429 MCU SPI connection.

issues that need resolving:

• AD7768 is used as SPI master, so STM32F429I SPI must be configured as SPI slave.

• The DRDY high pulse only lasts for one DCLK cycle, which is not a typical CS.

• After completing the output of all channel data bits, DCLK continues to output and DRDY is low.

Figure 6. AD7768 data bit reading in a timing solution.

• Configure one SPI port (such as SPI4) of the STM32F429 as a slave to receive data bits on MOSI at the DCLK rate.

• Connect the AD7768DRDY to the STM32F429 external interrupt input pin EXTI0 and the NSS (SPI CS) pin. The rising edge of DRDY will trigger the EXTI0 processing routine to enable the SPI slave to start receiving data bits at the first DCLK falling edge after DRDY goes low. Timing design is critical here.

• After all data from channel 0 to channel 7 are received, the SPI should be disabled to prevent additional invalid data from being read, because DRDY causes the SPI slave CS to go low and DCLK keeps toggling.

Figure 7. Configuring the SPI4 peripheral.

When the software is in interrupt mode, the DCLK can run up to 4 MHz to achieve an ODR of 8 kSPS. The software should enter the interrupt handler to start the SPI within one and a half DCLK cycle (375 ns). To make it easier for the software to enter the interrupt routine, the MCU can read the data on the DCLK rising edge, providing an extra half DCLK cycle time. However, the t5 DCLK rise to DOUTx invalid minimum is –3 ns (–4 ns at IOVDD = 1.8 V), so the propagation delay on DOUTx (>|t5| + MCU hold time) should be increased by PCB routing or buffering.

In the first solution, only DOUT0 is used to output all 8-channel data. Therefore, data reading limits the ADC throughput rate to 8 kSPS. As shown in Figure 1, outputting Channel 0 to Channel 3 on DOUT0 and Channel 4 to Channel 7 on DOUT1 can reduce the data transfer time. The connection of the serial line is shown in Figure 7. With this improvement, the ODR can easily reach 16 kSPS when the DCLK is 4 MHz.

Figure 8. The AD7768 outputs data through DOUT0 and DOUT1 to the STM32F429 MCU SPI connection.

The firmware can use polling mode instead of interrupt mode to reduce the time delay from the DRDY rising edge trigger to enabling SPI to receive data. This can achieve an ODR of 32kSPS when DCLK is 8MHz.

Figure 9. EXTI0 is in polling mode, and SPI4 and SPI5 receive the AD7768 data bits on DOUT0 and DOUT1.

Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory and between memory and memory. DMA can move data quickly without any MCU operation, which can free up MCU resources for other operations. The following is a design description of MCU SPI used as a slave to receive data through DMA.

Figure 10. EXTI0 is in polling mode and the SPI4 DMA receives the AD7768 data bits on DOUT0.

High throughput or multi-channel precision ADCs provide two, four or even eight SDO lines to the SPI port to read the code faster in serial mode. For microcontrollers with two or more SPI ports, these SPI ports can run simultaneously to speed up the reading of the code.

In the following use case, the 32F429IDISCOVERY uses SPI4 as the SPI master and SPI5 as the SPI slave to receive the EVAL-AD7606B-FMCZ data through DOUTA and DO UTB, as shown in Figure 8.

The AD7606B is a 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels, each of which includes analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter, and a 16-bit successive approximation register (SAR) ADC.

The AD7606B also has built-in flexible digital filters, low drift 2.5V precision references and reference buffers to drive ADCs and flexible parallel and serial interfaces. The AD7606B operates from a single 5V supply and supports ±10V, ±5V and ±2.5V true bipolar input ranges, and all channels can sample at a throughput rate of 800 kSPS.

Figure 11. Using the MCU SPI in master and slave mode to receive data through DOUTA and DOUTB.

Figure 12. SPI4 configured as master and SPI5 configured as slave

Figure 13 shows a digital interface screenshot of BUSY, SCLK, DOUTA, and DOUB when the AD7606B is running at 240 kSPS.

Figure 13. Oscilloscope capture of the AD7606B BUSY, SCLK, and data on DOUTA and DOUTB.

This article discusses methods for using a microcontroller SPI to access an ADC with a nonstandard SPI interface. These methods can be used directly or with slight modifications to control the ADC SPI; it can be used as an SPI master or with multiple DOUT lines to increase throughput.