An anti-aliasing filter for 24-bit ADCs
For many ADC applications, a simple RC filter placed at the buffer input provides adequate antialiasing filtering. For applications that require a higher order filter, an active filter is often used. The active components in such a filter must have sufficient bandwidth, fast settling speed, low noise, and low offset to not corrupt the signal before it reaches the ADC.
The LTC6363 is a differential operational amplifier optimized for driving low power SAR ADCs. The LTC6363 offers 500 MHz GBW, 780 ns settling to 4 ppm, 2.9 nV/√Hz and 100μV maximum offset voltage.
Figure 1 shows a 30kHz third-order filter using the LTC6363, which is optimized for use with the 1.5Msps/2Msps low power SARADC LTC2380-24 and has an integrated digital filter. The LTC2380-24 can average 1 to 65536 conversion results in real time, thereby improving the signal-to-noise ratio (SNR). Both inputs of this circuit can be driven differentially with a signal range of ±2.5 Vpp, or one input can be grounded and the other input driven with a signal up to ±5 Vpp.
Figure 1. 30kHz third-order filter driving 24-bit ADC LTC2380-24
Figure 2 shows the combined frequency response of the filter and ADC with a sampling rate of 1.5 Msps and the number of conversion results (N) to be averaged set to 1 and 8.
Figure 2. Combined frequency response of filter and ADC.
Figure 3. This is a PScope screenshot showing the FFT, SNR, and THD for the circuit in Figure 1 when N = 1.
Figure 3. PScope screenshot showing the FFT, SNR, and THD for the circuit in Figure 1 when N=1.
Figures 4 and 5 show the THD and SNR vs. input frequency for the circuit in Figure 1 for N = 1 and 8. Below a few kHz, the SNR and THD performance is close to the typical numbers in the datasheet. As the input frequency increases beyond a few kHz, the THD decreases smoothly.
Figure 4. Total harmonic distortion of the circuit shown in Figure 1 versus input frequency.
Figure 5. The signal-to-noise ratio of the circuit shown in Figure 1 varies with input frequency.
The LTC6363 family includes four fully differential, low power, low noise amplifiers with optimized rail-to-rail outputs to drive SAR ADCs. The LTC6363 is a stand-alone differential amplifier that typically uses four external resistors to set its gain. The LTC6363-0.5, LTC6363-1 and LTC6363-2 all have internal matched resistors to create fixed gain blocks with gains of 0.5V/V, 1V/V and 2V/V, respectively.
The precision resistors integrated in the LTC6363-0.5, LTC6363-1 and LTC6363-2 are designed with overall system performance in mind, achieving a balance between noise and linearity, and using laser trimmed factory calibration to achieve high precision, which is not only difficult to achieve with discrete device solutions, but also expensive to achieve. The initial gain accuracy is 45ppm (maximum) and the maximum variation over the entire temperature range is only 0.5ppm/oC. The common mode rejection ratio, which is usually limited by discrete resistor matching, has reached an excellent 94dB (minimum), equivalent to 0.002% resistor matching.
One of the challenges when driving high performance SAR ADCs is to find a suitable driver with similar power consumption levels while maintaining the ADC’s noise and linearity performance. The LTC6363 family excels in this regard. For example, the LTC2378-20 20-bit SAR ADC consumes 21mW at 1Msps, and the LTC6363 family has negligible impact on the ADC’s performance with noise and linearity, while consuming only 19mW, which is comparable to the ADC’s power consumption. Now, with the LTC6363-0.5, LTC6363-1 and LTC6363-2, you can get this same ADC driving performance, plus the added precision provided by precision integrated resistors, all in the same compact MSOP8 package.
——Linear Products and Solutions Design Manager at ADI
Maziar Tavakoli
For more information about the LTC6363 differential operational amplifier series, please click "Read More"
京公网安备 11010802033920号