To understand the growth of power domains and supplies, we need to trace the history of ADCs. Early ADCs sampled very slowly, in the tens of MHz, and the digital content was minimal or nonexistent. The digital portion of the circuit was primarily concerned with how to transmit data to the digital receiving logic—an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The process nodes used to fabricate these circuits were large in geometry, around 180 nm or larger. Good enough performance was achieved using a single voltage rail (1.8 V) and two distinct domains (AVDD and DVDD, for analog and digital domains, respectively).
As silicon processing technology improves, transistor geometries continue to shrink, meaning more transistors (and features) can be packed into each mm
2
of area. However, ADCs are still expected to achieve the same (or better) performance as their predecessors.
Today, the design of ADCs takes a multifaceted approach, where:
1. Sampling speed and analog bandwidth must be improved;
2. Performance must be the same or better than the previous generation;
3. Incorporate more on-chip digital processing functions to assist the digital receive logic.
The following will further discuss each of these characteristics and the challenges they pose to chip design.
In CMOS technology, the most common way to increase speed (bandwidth) is to make transistor geometries smaller. Using finer CMOS transistors reduces parasitic effects, which helps increase transistor speed. The faster the transistor, the wider the bandwidth. The power consumption of a digital circuit is directly related to the switching speed and the square of the power supply voltage, as shown in the following equation:
|
in:
P is power consumption
C
LD
is the load capacitance
V is the power supply voltage
fSW
is
the switching frequency
|
As geometries get smaller, circuit designers can make their circuits faster while consuming the same power per transistor per MHz as the previous generation. Take the AD9680 and AD9695, which were designed using 65 nm and 28 nm CMOS technologies, respectively. At 1.25 GSPS, the AD9680 and AD9695 consume 3.7 W and 1.6 W, respectively. This means that a circuit built on a 28 nm process consumes half the power of the same circuit built on a 65 nm process, given roughly the same architecture. Therefore, a 28 nm process circuit can run twice as fast as a 65 nm process circuit while consuming the same power. The AD9208 illustrates this well.
Abundance is the most important
The need for wider sampling bandwidths has driven the industry to finer geometries, but expectations for data converter performance, such as noise and linearity, remain. This presents unique challenges for analog design. An undesirable consequence of the move to smaller geometries is the reduction in supply voltages, which significantly reduces the margin required to develop analog circuits to operate at high sampling rates and maintain the same noise/linearity performance. To overcome this limitation, circuits are designed with different voltage rails to provide the required noise and linearity performance.
For example, in the AD9208, the 0.975 V supply powers the circuits that need to switch quickly. This includes the comparator and other related circuits, as well as the digital and driver outputs. The 1.9 V supply powers the reference and other bias circuits. The 2.5 V supply powers the input buffers, which must have high headroom to operate at high analog frequencies. It is not necessary to provide a 2.5 V supply to the buffers, which can also operate at 1.9 V. Reducing the voltage rail will result in degraded linearity performance.
Digital circuits do not require margin, as the most important parameter is speed. Therefore, digital circuits are usually run at the lowest supply voltage to gain the advantages of CMOS switching speed and power consumption. This is evident in newer generations of ADCs, where the lowest voltage rail has been reduced to 0.975 V. Table 1 below lists some common ADCs over several generations.
Table 1: Product comparison
As the industry moves to deep submicron technology and high-speed switching circuits, functional integration is also increasing. Take the AD9467 and AD9208 as examples. The AD9467 uses a 180 nm BiCMOS process, while the AD9208 uses a 28 nm CMOS process. Of course, the noise density of the AD9467 is about -157 dBF S/Hz, while the noise density of the AD9208 is about -152 dBF S/Hz. However, if you take the data sheet and do a simple calculation, take the total power consumption (per channel) and divide it by the resolution and sampling rate, you can see that the power consumption of the AD9467 is about 330μW/bit/MSPS, while the AD9208 is only 40μW/bit/MSPS.
Compared to the AD9467, the AD9208 has a higher sampling rate (3 GSPS vs. 250 MSPS) and a much higher input bandwidth (9 GHz vs. 0.9 GHz), and integrates more digital features. The AD9208 does all of this while consuming only about 1/8 the power per bit per MSPS. Power per bit per MSPS is not an industry standard specification, but serves in this case to highlight the benefits of using smaller process geometries in ADC design. When ultrafast circuits are running in close proximity, there is always a risk of coupling or chatter between the various blocks.
To improve isolation, designers must consider various coupling mechanisms, the most obvious being through shared power domains. If the power domains are as far away from the circuit as possible, there is little chance of chatter between digital and analog circuits that share the same voltage rail (0.975 V for the AD9208). In silicon, the power supplies are already separated, as are the grounds. This treatment of isolated power domains continues in the package design. The resulting partitioning of different power domains and grounds within the same package is shown in Table 2, which uses the AD9208 as an example.
Table 2: AD9208 power and ground domains
Figure 1. AD9208 pin configuration (top view)
This can cause panic among system designers. At first glance, the data sheet gives the impression that these domains need to be treated separately to optimize system performance. The situation is not as dire as it seems, and the purpose of the data sheet is simply to call attention to the various sensitive domains so that system designers can focus on the PDN (power delivery network) design and partition them appropriately. Most power and ground domains that share the same supply rail can be merged, so the PDN can be simplified. This results in a simplified BOM (bill of materials) and layout. Depending on the design constraints, Figure 2 and Figure 3 show two PDN design approaches for the AD9208.
Figure 2. AD9208 pin configuration (top view)
Figure 3. AD9208 PDN with dc-to-dc converters powering all domains.
With adequate filtering and layout separation, the domains can be arranged to maximize ADC performance while reducing BOM and PDN complexity. Kelvin connections for each ground domain will also improve isolation. From a netlist perspective, there is still only one GND net. The board can be divided into different ground domains to provide adequate isolation. In the AD9208-3000EBZ, the evaluation board for the AD9208, different ground partitions form Kelvin connections on layer 9. Figure 4 shows a cross-section of the 10-layer PCB (printed circuit board) AD9208-3000EBZ, which shows the different GND connections.
Figure 4. Cross section of the AD9208-3000 EBZ PCB underneath the AD9208.
Therefore, just because the AD9208 data sheet shows all of these domains, it does not mean that they must all be separated on the system board. Understanding the system performance goals and the ADC target performance plays an important role in optimizing the PDN for the ADC. Using smart partitioning on the board to reduce unnecessary ground loops is key to minimizing crosstalk between domains, and appropriately sharing power domains while meeting isolation requirements will simplify the PDN and BOM.
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