Empirical multi-channel phase noise model validated in 16-channel demonstrator

Phase noise is an important performance metric for all RF system designs. In large multi-channel RF systems such as phased arrays, where the channels are correlated with each other, one of the goals is to improve dynamic range at the array level using correlated combinations of distributed receivers and transmitters. Achieving this goal presents a systems engineering challenge: decomposing the relevant and uncorrelated noise terms in the system. This article presents a systematic approach to estimating phase noise for a 16-channel RF demonstrator to help system engineers develop an analytical method for evaluating the noise performance of large systems.

Signals within a phased array contain noise terms that are uncorrelated on the channel and noise terms that are correlated on the channel. The additional noise of distributed components is simply uncorrelated. However, signals shared by distributed components create associated noise components. The challenge is: how to quickly identify relevant noise terms in the architecture. Common or shared content will cause correlated noise in the channel. Examples include shared LO, clock, or power supply. As system complexity increases, resolving these noise terms becomes difficult. Therefore, it would be of great help to system designers building next-generation systems if they could use an intuitive method to redraw the architecture from a noise perspective and quickly identify relevant noise contributions.

In this article, we demonstrate the method using a 16-channel S-band system and prove that the phase noise of various other channel combinations can be predicted relatively accurately using only a few empirical measurements. The key point for this kind of empirical model is that some actual measurements are needed. It is not easy to go directly from component simulation to large multi-channel phase noise estimation (with decent accuracy). However, using only a few measurements, it is possible to extract both correlated and uncorrelated noise terms, making multi-channel estimates more accurate. Our measurements match the estimates (within 1 dB) to measurements from a 16-channel S-band demonstrator.

Figure 1. 16-channel demonstrator: This platform contains four AD9081 chips. Each AD9081 chip contains 4 RF DACs and 4 RF ADCs, providing a total of 16 transmit and 16 receive channels.

When combining signals in free space or RF signal processing, the added noise to each signal is

where c represents the correlation coefficient, ranging from –1 to +1. If c = –1, the noise is canceled; if c = 0, the noise is uncorrelated; if c = 1, the noise is perfectly correlated.

Assuming the calibration is used to combine the main signals consistently, the main signal will increase at the 20logN level, where N is the number of channels.

• If the noise term is uncorrelated (c = 0), the noise will increase by 10logN. As the signal level increases at a rate of 20logN (10logN greater than the noise rate), the SNR will improve by 10logN.

• If the noise term is correlated (c = 1), the noise, like the signal, also increases at a rate of 20logN, so the SNR does not improve. This is not an ideal result for a distributed system.

• In noise cancellation circuits, a negative correlation coefficient is produced. This case is recorded to supplement formula 1, but will not be elaborated.

In fact, large distributed systems contain noise components that are partially correlated in the channels. Therefore, there is a need to develop a practical and intuitive approach to system-level noise models.

To evaluate the latest high-speed data converters in a multi-channel environment, a 16-channel direct S-band RF sampling platform was developed. The platform contains four AD9081 MxFE ^® (mixed-signal front-end) chips. Each AD9081 chip contains 4 RF DACs and 4 RF ADCs, providing a total of 16 transmit and 16 receive channels.

The 16-channel evaluation platform is named Quad-MxFE because it has 4 MxFE chips. The overall block diagram and board picture are shown in Figure 1 and Figure 2 respectively.

The 16-channel development platform block diagram shown in Figure 1 shows its functional scope. As you can see from the figure, it is not initially clear how to view the fraction of noise caused by correlated and uncorrelated noise components. There is a need to provide a way to consider system architecture from a noise perspective. A sketch can be used to indicate noise terms that are present for all channels, noise terms that are relevant to certain groups of channels, and noise terms that are completely independent of channels. Figure 3 is an illustration of the 16-channel development platform, dividing the noise terms into three categories.

• Clock Noise: Quad-MxFE offers options for multiple clock configurations. The specific configuration used needs to be accounted for in the phase noise model. Our tests used a common low phase noise clock across all channels, or four independent distributed ADF4371 phase-locked loop (PLL) frequency synthesizers as clock inputs to each of the four MxFEs. For a single common clock, this noise is associated with all 16 combined channels. For the case of using 4 ADF4371 PLLs (1 for 1 MxFE), the PLL noise is correlated with each MxFE but not across MxFEs, whereas the reference noise is correlated across all channels.
  

• Peter Delos' article titled "System-Level LO Phase Noise Model for Phased Arrays with Distributed Phase-Locked Loops" summarizes analytical methods for dealing with distributed phase-locked loops. The analysis used in this reference illustrates the noise components at the reference frequency, distributed systems, and PLL circuits, and illustrates the impact of PLL loop bandwidth.

• Correlated noise per MxFE: This is the noise from the MxFE, associated with each channel in the MxFE. In this analysis, the associated noise for each MxFE includes additive noise common in each chip, as well as power supply effects common in the channels within the chip.

• Uncorrelated noise per channel: This is the difference in noise from different channels. Includes DAC core and all amplifier additive phase noise. In Equation 2, this term is labeled TXNoise.

Based on the contribution components of the phase noise, the total phase noise can be calculated as follows.

Next, some additional details are provided on how to simplify this model to fit this testbed.

• Power supply effect: In low phase noise designs, power supply phase noise is an important factor to consider. For methods that can be used to solve power supply noise problems, see the articles "Power Supply Modulation Ratio Demystified: What's the Difference Between PSMR and PSRR" and "Improved DAC Phase Noise Measurement Enables Ultra-Low Phase Noise DDS Applications." In this article's analysis, the power supply The effects are treated as subterms of the noise term captured in Equation 2. If power supply noise is the dominant source of phase noise in the IC and is present in all channels, this effect needs to be accounted for as a correlation term just like the correlated noise due to each MxFE used earlier in this article.

• Reference Oscillator Noise: In large systems, the reference oscillator noise contribution needs to be apportioned as described in the article "System-Level LO Phase Noise Model for Phased Arrays with Distributed Phase-Locked Loops". This test bench uses an extremely low phase noise reference, which produces a noise component that is much lower than the other components and is not specifically noted in the noise summation equation.

After Equation 2 introduces the combined phase noise model, the next question is "How do you get the noise contribution component values ​​used in the equation?" When using the Quad-MxFE test bench, the measured values ​​can be used to extract the required information:

• Absolute phase noise of clock source

• Additional phase noise of channels with different MxFE

• Additional phase noise of the same MxFE channel

The test setup and measurements are shown in Figure 4. Figure 4(b) and Figure 4(c) provide additional noise measurements with the common clock source removed. When measuring the additive phase noise in a single MxFE, the correlated noise across channels in the MxFE is also removed. However, when measuring additive phase noise across the MxFE, the measurement will include the associated noise in the MxFE.

Figure 4. Use three measurements to validate the phase noise model.

The final step is to change the measured data into the three terms used in Equation 2 as follows:

1. Clock noise = clock phase noise measurement (Figure 4(a)) + 20log (F _OUT /FCLOCK)

2. Correlated noise due to each MxFE = Additive phase noise across the MxFE (Figure 4(b)) – Additive phase noise of the universal MxFE (Figure 4(c)). Note that when doing this calculation, you need to first convert to linear power, then subtract, and then reconvert to dB, which gives 10log(10^(added phase noise across MxFE/10) – 10^(added phase noise across MxFE /10))

3. TxNoise = additive phase noise of universal MxFE (Figure 4(c)).

An additional note about additive phase noise measurements: We found that the noise terms for items 2 and 3 above also expanded with frequency when using this hardware. When converting to other frequencies, an additional 20log(F _OUT /F _MEAS ) is required. This is not true for all hardware and each design needs to be evaluated individually.

When performing this measurement, a low-noise 12 GHz clock is used throughout the 16-channel demonstrator. The clock source is SMA100B, which is injected into the external clock injection node as shown in Figure 1. The conditions shown apply for a 3.2 GHz transmit output frequency.

As can be seen from Figure 5(b), the correlated noise across MxFE is the most dominant contribution component. After adding MxFE to the system, this noise contribution component will increase and will then be limited by the universal clock source. Depending on the curve shape of each contributing component, just adding a few points to the curve is not enough to derive an accurate prediction, so we found it best to use the data in Figure 5(b) directly in Equation 2. Then, a series of calculations are performed to validate the model. As can be seen from Figures 6 to 8, the accuracy of the prediction values ​​provided by this model is very high.

Figure 6. Measured values ​​and model predictions for 16 channels at 3.2 GHz.

Figure 7. Measured values ​​and model predictions for 8 channels at 3.2 GHz. The difference between the two figures is how the MxFE shares the transmit channel.

A few observations about measured and predicted values ​​are worth noting. In many cases, the predicted values ​​are almost identical to the measured values. In some cases, the measured values ​​were slightly lower than the predicted values. We acknowledge this but cannot give an accurate description. The plot on the left side of Figure 8 provides a potential indicator. When zooming in on these plots, we see that the predicted values ​​match the two measured examples, but the values ​​for the measured case are slightly higher. It may be that in the AD9081 chip, the related noise caused by each MxFE is not exactly the same, resulting in some differences. Some simplifying assumptions described in Section 5 may also be responsible for the differences. In these examples, the predictions were quite accurate, and we believe this approach is valid for this design.

In this measurement, a separate ADF4371 was used for each of the 4 MxFEs, as shown in Figure 1. The ADF4371 is locked using a low phase noise 500 MHz reference and is configured to provide a 12 GHz output. Figure 9 shows the measured values ​​and noise contribution components used to validate the model.

Figure 9. A) Measurements used to validate the phase noise model when using a standalone ADF4371 chip as the clock input source, and b) calculated phase noise contributions used in the model. This is the case for distributed PLLs per MxFE.

In this example, the PLL is the dominant noise source, and the noise component contributed by MxFE is much lower than the clock noise. As shown in Figure 10, depending on the number of PLLs used in the distributed system, the combined noise improves accordingly.

This paper shows an empirical model that can predict phase noise in combined channels with reasonable accuracy. The prerequisite for using this method is to first view the system from the perspective of the noise source and redraw the block diagram to see what is relevant and what is not.

We also highlight the word "empirical", which means that the proposed method is verified by observation or experience, rather than based on theory or pure logic. For the phase noise example, the point made is that to evaluate the area and contributing components, some measurements and observations need to be used. Once you understand the above, you can systematically calculate system noise.

The data and formulas used in this article apply only to this hardware to a certain extent and are based on the observations described previously. However, this approach can be used with any multi-channel system. A more general block diagram is shown in Figure 11. By first introducing the system reference oscillator, and then plotting the clock and LO distributions against the channel-level hardware, you can more intuitively view the sources of noise contributions in large systems.

Figure 11. Schematic diagram of a general phased array drawn from a phase noise perspective. Each signal contains noise terms, which are a combination of noise components distributed in the array. After redrawing the system diagram from this perspective, it is easier to show traces of correlated and uncorrelated noise at the system level. If the designer first plots the system reference oscillator and then plots the clock and LO distributions against the channel-level hardware, the sources of noise contributions in large systems can be more visually displayed.