What are the most important timing considerations for building low power precision signal chain applications using sigma-delta ADCs?
Latest update time：2022-11-24 09:18
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"Time is of the essence" - This old idiom can be applied to any field, but when applied to the sampling of real-world signals, it is a mainstay of our engineering discipline. When trying to reduce power consumption, achieve timing goals, and meet performance requirements, one must consider which type of ADC architecture to choose for the measurement signal chain: Σ-Δ or successive approximation register (SAR). Once a specific architecture is selected, the system designer can create the required circuitry to achieve the necessary system performance. At this point, designers need to consider the most important timing factors for their low-power precision signal chain.
Figure 1. Signal chain timing considerations
Need high speed: Should I choose SAR type or Σ-Δ type for low-power signal chain?
We will focus on precision low-power measurements and signals with measurement bandwidths below 10 kHz (such as temperature, pressure, and flow), but many of the topics covered in this article can also be applied to measurement systems with wider bandwidths.
In the past, when exploring low-power systems, designers would choose sigma-delta ADCs to achieve higher accuracy measurements of slow-moving signals. SARs are considered more suitable for high-speed measurements that require converting more channels, but new SARs such as the AD4630-24 are entering the high-precision realm where sigma-delta ADCs have traditionally been used, so this is not a hard and fast rule. For real-world examples of ADC architectures, let’s look at two low-power products and consider the timing associated with the ADC signal chain architecture: the AD4130-8 sigma-delta ADC and the AD4696 SAR ADC, as shown in Table 1.
Table 1. Ultra-low power ADC
Sampling frequency or output data rate?
The SAR converter samples the input, capturing the signal level at a known point in time. The initial sample (and hold) phase is followed by the conversion phase. The time required to obtain results strongly depends on the sampling frequency.
The sigma-delta converter samples at the modulator frequency. The modulator will oversample, sampling at a rate well above the Nyquist frequency of the input signal. The additional frequency span allows noise to be shifted to higher frequencies. The ADC then uses a process called decimation on the modulator output, which reduces the sampling rate in exchange for greater accuracy. It is done through a digital low-pass filter, which is equivalent to an averaging operation in the time domain.
Different technologies have different ways of obtaining conversion results. SAR product documentation uses the concept of sampling frequency (fSAMPLE), while data sheets for Σ-Δ products use output data rate (ODR). When discussing these architectures in detail relative to time, we will guide the reader to distinguish between the two.
Figure 2. Comparison of SAR (ƒ
SAMPLE
) and Σ-Δ (ODR)
For a multiplexed ADC that performs one conversion on multiple channels, the time required to perform the conversion on all channels (including settling time, etc.) is called the throughput rate.
The first timing consideration in the signal chain is the time required to bias/excite the sensor and power up the signal chain. Voltage and current sources need to be turned on, sensors need to be biased, and start-up time specifications need to be considered. For example, the AD4130-8 on-chip voltage reference has a turn-on settling time of 280 µs for a specific load capacitance on the reference pin. The on-chip bias voltage (which can be used to excite the sensor) has a startup time of 3.7 µs per nF, but this depends on the capacitance connected to the analog input pin.
After studying the power-up time in the signal chain, we need to understand the timing considerations related to the ADC architecture. We will first focus on the measurement signal chain centered on a sigma-delta ADC in ultra-low power applications, as well as the important timing considerations associated with such ADCs. SAR and sigma-delta signal chains have some overlap in aspects that impact timing, such as using techniques to minimize microcontroller interaction time, thereby achieving system-level power improvements.
Signal Chain Timing Considerations When Using Sigma-Delta ADCs
If the ADC chosen is a sigma-delta type rather than a SAR type, a specific set of timing factors need to be considered. When looking at the signal chain, the main areas to explore are analog front-end timing, ADC timing, and digital interface timing, as shown in Figure 1.
Analog front-end timing considerations
We will explore these three modules separately, starting with the Analog Front End (AFE). AFEs may vary depending on the type of design, but there are some common aspects that apply to most circuits.
Figure 3. AFE Σ-Δ timing considerations
The AD4130-8 is part of the Precision Low Power Signal Chain product group and is specifically designed with a rich feature set to achieve high performance while reducing power consumption. Some of these features include on-chip FIFO, intelligent channel timing controller and duty cycle control.
The AD4130-8 is an ultralow power sigma-delta ADC from Analog Devices. The ultralow current is impressive considering that it contains many key signal chain building blocks on chip, such as on-chip voltage reference, programmable gain amplifier (PGA), multiplexer, sensor excitation current or sensor bias voltage.
The device's AFE includes an on-chip PGA that minimizes analog input current, eliminating the need for an external amplifier to drive the input. The digital filter after oversampling ensures that the bandwidth is primarily controlled by the digital filter. The AD4130-8 provides multiple on-chip sinc3 and sinc4 filters, plus filters for 50 Hz and 60 Hz noise rejection. The sinc3 and sinc4 digital filters require an external anti-aliasing filter to supplement them. The purpose of this anti-aliasing filter is to limit the amount of bandwidth of the input signal. This is to ensure that noise (such as noise with a rate of change of the modulator frequency f
MOD
) does not alias into the passband and conversion results.
Figure 4. AD4130 Σ-Δ simplified system module
Figure 5. Simulation of combined external and internal filtering.
Anti-aliasing filter
Higher order anti-aliasing filters can be used, but a first-order, single-pole, low-pass filter usually suffices. The filter is designed based on sampling the target signal, and Equation 1 determines the 3 dB bandwidth of the filter:
When choosing capacitor and resistor values, higher resistor values are preferable but may increase noise, while lower capacitor values have a limit beyond which the ratio of pin capacitance to external capacitance becomes relevant .
It is important to determine the time it takes for the circuit to charge based on the maximum voltage step that can be seen across this capacitor.
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