What TI DSP Power Knows

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What TI DSP Power Knows [Copy link]

Multicore DSP implementations require intelligent power management given the plethora of voltage and current requirements for the core, memory, I/O, and other rails. An important performance benchmark for the DSP core voltage supply is the ability to adjust VCORE in real time based on DSP usage and environmental conditions. VCORE commands are typically provided in a digital format that the power supply should be able to interpret at any time. The VCORE rail typically has the largest current specification, and a small power solution that balances efficiency and size is also important. The key is to implement this voltage identification (VID) function using a low-cost interface between the DSP and the analog PWM stage.

Therefore, the following figure provides an illustration of a multi-core DSP with the core power rail labeled CVDD.

LM10011 and analog PWM power stage

The LM10011 not only captures the VID information present on the DSP VCNTL interface, but also sets the current DAC output connected to the feedback (FB) pin of the power stage circuit. In 6-bit mode, it provides 64 current settings with a resolution of 940nA and an error accuracy of better than 1%. In this example, CVDD is determined by the DSP as a voltage level between 0.9V and 1.1V, supporting a step resolution of 6.4mV. Resistor RSET determines the CVDD voltage at startup without the need for a level converter or glue logic. The LM10011 can be connected to any voltage, current, or DCAP mode PWM regulator with an FB input.