How much do you know about the alias-free characteristics of CTSD ADC?

In many applications such as sonar arrays, accelerometers, and vibration analysis, signals outside the bandwidth of the target signal will be monitored, and these signals are called interferers. For signal chain designers, the key challenge is that ADC sampling causes these interferers to alias into the target signal bandwidth (in-band), resulting in performance degradation. In addition, in applications such as sonar, in-band aliased interferers may be misunderstood as input signals, resulting in misjudgment of objects around the sonar. The aliasing suppression solution is one of the reasons why traditional ADC signal chain design is extremely complex. The CTSD ADC has its own aliasing suppression feature, which brings a new simplified solution. Before exploring this breakthrough solution, let's first understand the concept of aliasing.

To understand the concept of aliasing, let's quickly review the Nyquist sampling criterion. We can analyze signals in the time domain or the frequency domain. In the time domain, sampling an analog signal can be mathematically represented as a signal multiplication operation, for example, x(t) represents a pulse train δ(t) with a duration of T _s .

Figure 1. Time domain representation of the sampling process.

Likewise, in the frequency domain, the sampled output can be expressed using a Fourier series as:

It can be seen from Formula 1 that if the frequency axis is expanded, an image of the input signal will be formed at each integer multiple of the sampling frequency _{fs .}

Figure 2. Representation of X(f) after sampling at different sampling frequencies

Equation 1 shows that at a frequency f = n × fs _- fIN _, where n = 0, ±1, ±2, ..., the signal content X(f) will appear at fIN after sampling, similar to the undersampling scenario in Figure 2, which shows the sampling phenomenon under various conditions.

Figure 3. (A) Understanding aliasing based on sampling criteria and (b) using an antialiasing filter to attenuate aliased frequencies.

In summary, the Nyquist criterion states that any signal greater than half the sampling frequency will be folded or reflected back to frequencies below fs _/ 2 and may fall into the frequency band of interest.

Assume that the ADC samples at frequency fs _, and there are two out-of-band tones/interference sources in the system, namely f1 and f2 at the ADC input _, as _shown in Figure 3. According to the Nyquist criterion, we can infer that since the frequency of the tone f1 is less than fs _{/ 2} , its frequency remains unchanged after sampling. When the frequency of the tone f2 _is greater than fs _/ 2, it will alias in the target frequency band _{fbw_in} and degrade the performance of the ADC in this area, as shown in Figure 3a.

This theory also applies to noise above fs _/ 2, which can also fold and appear in-band, increasing the in-band noise floor and degrading performance.

To avoid this performance degradation caused by out-of-band (OOB) tones or noise folding in, a simple solution is to use a low-pass filter to attenuate the signal content above fs/2 before sampling by the ADC. _This filter is called an anti-aliasing filter (AAF). Figure 3b shows the transfer function of a simple AAF and the attenuation of the aliased tones at frequency f2 _before they are folded in-band. The main characteristic parameters of this AAF are the filter order and the –3 dB corner frequency. They are determined by the passband flatness, the absolute attenuation required at a specific frequency (such as the sampling frequency), and the required attenuation slope outside the input bandwidth (also called the transition band). Some common filter architectures include Butterworth, Chebyshev, Bessel, and Sallen-Key, which can be implemented using passive RCs and op amps. Filter design tools are available to help signal chain designers design AAFs based on given architectures and requirements.

Let’s take an application example to understand the requirements of anti-aliasing filters. In a submarine system, a sonar sensor transmits sound waves and analyzes the underwater echoes to estimate the position and distance of surrounding objects. The input bandwidth of this sensor is 100 kHz, and the system considers the signal tone with an amplitude >–85 dB detected at the ADC input as a valid echo source. Therefore, any interference from out-of-band needs to be attenuated by at least –85 dB by the ADC to avoid being detected as an input by the sonar system. In the next section, we will build and compare aliasing suppression solutions for different ADC architectures for these requirements.

In traditional ADC architectures, such as successive approximation register (SAR) and discrete time Σ-Δ (DTSD) ADCs, the sampling circuitry is located at the analog input of the ADC, which dictates the need to use an AAF before the ADC input, as shown in Figure 3b.

AAF Requirements for SAR/Nyquist Sampling ADCs

The sampling frequency of a SAR ADC is typically set at 2 or 4 times the analog input frequency (f _{IN ). The AAF of this ADC requires a narrow transition band outside the frequency f IN} , which means a high-order filter is required. As can be seen in Figure 4, a SAR ADC with a sampling frequency of about 1 MHz requires a fifth-order Butterworth filter to achieve –85 dB rejection at frequencies greater than 100 kHz. For the filter implementation, as the order of the filter increases, the number of passive and operational amplifiers required also increases. This means that the AAF of the SAR ADC requires a significant power and area budget in the signal chain design.

AAF Requirements for DTSD ADC

Σ-Δ ADCs are oversampled ADCs, where the sampling frequency is much higher than the analog input frequency. The aliasing region to consider in the AAF design is fs _± fIN _. The filter transition band is required to be from fIN _to very high fs _. This transition band is wider than the SAR ADC AAF, which means that a lower order AAF is required. As can be seen in Figure 4, for a DTSD ADC with a sampling frequency of 6 MHz, a second-order AAF is generally required to achieve –85 dB aliasing rejection at frequencies around fs – 100 kHz _.

In real applications, interference or noise may be present anywhere in the frequency band, not just around the sampling frequency fs _. Any frequency tone below fs/2 (such as the tone at frequency f1 in Figure 3 _{) will} not appear in the band and will not degrade the ADC performance. Although the AAF can attenuate the tone f1 _to some extent, it will still be present in the ADC output as unwanted information that the external digital controller must process. Can this tone be further attenuated so that it no longer appears in the ADC output? One solution is to use an AAF with a narrow transition band outside of frequency fIN _, but this increases the complexity of the filter design. Another solution is to use an on-chip digital filter in the sigma-delta modulator loop.

Figure 4. AAF complexity, ADC architecture, and target frequency band.

Figure 5. STF of DTSD ADC with AAF on the front end and digital filter on the back end.

Digital filter of the ∑-∆ modulator loop

In Σ-Δ ADCs, the modulator output contains a lot of redundant information due to oversampling and noise shaping, which requires a lot of processing by the external digital controller. This redundant information processing can be avoided if the modulator data is averaged, filtered, and provided at a lower output data rate (ODR), typically 2 × f _IN . The sample rate can be converted from f _IN to the desired lower ODR using a decimation filter. The use of digital filters to achieve sample rate conversion will be discussed in a future article, but the key point here is that discrete-time Σ-Δ modulators are usually used in conjunction with an on-chip digital filter. The combined signal-to-interference transfer function (TF) of a modulator with an analog filter on the front end and a digital filter on the back end is shown in Figure 5.

In summary, the AAF of the DTSD ADC is designed based on the required attenuation of the tones around the aliasing region f _{s . The tones in the non-aliasing region (e.g., f 1} ) are completely attenuated by the on-chip digital filter.

Back-end digital filter and front-end analog filter

SAR ADCs require AAFs with narrow transition bands, while Σ-Δ ADCs require digital filters with narrow transition bands. Digital filters have low power consumption and are easy to integrate on-chip. In addition, programming the order, bandwidth, and transition band of digital filters is much simpler than that of analog filters.

The advantage of oversampling is that it allows the combination of wide transition-band analog filters and narrow transition-band digital filters in the back end to provide a solution with better power consumption, size, and anti-interference performance.

Although the AAF requirement is relaxed with the DTSD ADC, the design complexity is increased to meet the settling time requirement after each sample to avoid degradation of the signal chain performance. The challenge for the signal chain designer is to fine-tune the AAF and find a balance between the need for alias suppression and the need for output stability.

The new precision CTSD ADC simplifies signal chain design by eliminating the need for front-end analog filter design.

A first-order CTSD modulator built from a closed-loop resistive inverting amplifier is shown in Figure 6. The CTSD modulator follows the same oversampling and noise shaping concepts as its DTSD modulator equivalent to achieve the desired performance, and has resistive inputs instead of switched capacitor inputs. The modulator building block consists of a continuous-time integrator followed by a quantizer to sample and digitize the integrator output, and a feedback DAC to close the input loop. Any noise at the quantizer input is noise shaped by the gain transfer function of the integrator.

Figure 6. (a) Building blocks of the CTSD modulator loop and (b) simplified block diagram for mathematical analysis.

A simplified block diagram of the CTSD modulator loop is drawn using the following mathematical model:

• The integrator transfer function is generally referred to as H(f), also known as the loop filter. For a first-order integrator, H(f) = 1/2πRC.

• The functions of an ADC are sampling and quantization. Therefore, the simplified ADC model used for analysis uses a sampler followed by an additive quantization noise source.

• A DAC is a module that multiplies its input by a constant during the current clock cycle. So, it is a module that has a constant impulse response during the sampling clock cycle and a zero impulse response the rest of the time.

The equivalent block diagram of these simplified models is shown in Figure 6b and is widely used in ∑-∆ performance analysis. The transfer function from V _IN to V _{OUT is called the signal TF (STF), and the function from Q e} to the output is called the noise TF (NTF).

A plausible explanation for the inherent alias rejection of the CTSD modulator loop is that the sampling does not occur directly at the modulator input, but after the loop filter H(f), as shown in Figure 6a. To understand the full picture, the concept will be understood using a linear model without a sampler and the analysis will be expanded to include a loop with a sampler.

Step 1: Implement STF and NTF analysis using linear models

To simplify the analysis, the sampler is ignored and the linear mode should be as shown in Figure 7. The STF and NTF of this loop can be expressed as

According to formula 3, STF can be rewritten as

The target frequency bandwidth is low frequency, which can be mathematically represented as f→0, and high frequency can be represented as f→∞. The magnitude (in dB) of STF and NTF is a function of frequency, as shown in Figure 7.

Figure 7. (a) Linear model used to simplify analysis, (b) STF(f) = H(f) × NTF(f).

Figure 8. (a) Block diagram of a CTSD modulator loop, input = 0 V, (b) NTF of the modulator loop.

Figure 9. The modulator loop has been rearranged to show its inherent alias rejection properties.

The NTF is similar to a high-pass filter, and the STF is similar to a low-pass filter, with a flat 0 dB amplitude in the frequency band of interest and an attenuation at high frequencies comparable to the AAF TF. From a mathematical point of view, the signal passes through a low-pass filter configuration H(f) with high gain and is then processed by the NTF loop. Now, after understanding the NTF block diagram, we can go a step further and understand the loop with the sampler.

Step 2: Block Diagram of NTF

The modulator loop block diagram can be rearranged as shown in Figure 8a to represent the NTF when the input, V _{IN ,} is set to 0 V. When a sampler is included in the loop, the NTF response is similar to the linear model, but replicas are displayed at multiples of f _{s , as shown in Figure 8b.}

Step 3: Re-layout the modulator loop to visualize the pre-filtering operation

The input to output transfer function does not change if the loop filter H(f) and the sampler of the modulator loop are moved to the input and the feedback is as shown in Figure 9. The right side of the rearranged block diagram shows the NTF.

Similar to the linear model in step 1, in the sampling equivalent system, the input signal passes through a high gain H(f) and is then sampled and processed by the NTF loop. The signal passes through the transverse section after the loop filter and forms a low-pass filter configuration before sampling. This configuration results in the inherent aliasing rejection of the CTSD modulator. Therefore, the STF of the CTSD modulator loop is shown in Figure 9.

Step 4: Complete STF Using a Digital Filter

To reduce unwanted high-frequency information, the CTSD modulator is used in conjunction with an on-chip digital decimation filter, and the combined aliasing suppression TF is shown in Figure 10. Aliases near _fs are attenuated using the inherent aliasing suppression characteristics of the CTSD, while intermediate interferers are attenuated by the digital filter.

Figure 4 compares the AAF order required to achieve –80 dB alias rejection for the SAR ADC, DTSD ADC, and CTSD ADC at the sampling frequency and input signal bandwidth. When using the SAR ADC, the AFF has the highest order and therefore the highest complexity, while the CTSD ADC does not require an external AAF because its design has inherent alias rejection performance.

In some multi-channel applications such as sonar beamforming and vibration analysis, the phase information between channels is very important. For example, the phase between channels needs to be precisely matched to an accuracy of 0.05° at 20 kHz.

For traditional ADC signal chains, passive RCs and op amps are used in AAF designs. The filter causes a certain amplitude and phase rolloff in the band, which is a function of the corner frequency. For good channel-to-channel phase matching, all channels need to have the same rolloff, which means that the filter corner frequency of each channel needs to be carefully controlled and matched. A second-order Butterworth filter designed to achieve –80 dB rejection at 16 MHz (sampling frequency) and 160 kHz f _3dB (input bandwidth) may have a phase mismatch of ±0.15° at 20 kHz, and the error tolerance may be as low as 1% of the absolute value of the RC. The available RC passive components with smaller error tolerance are limited and increase the bill of materials (BOM).

Since no AAF is required in the CTSD ADC signal chain, channel-to-channel amplitude and phase matching is naturally achieved within the band of interest. Phase mismatch is limited by the on-chip mismatch of the analog modulator loop design and can be as low as ±0.02° at 20 kHz.

Figure 10. CTSD modulator loop with back-end digital filter.

The AD4134 data sheet, a precision ADC based on the CTSD ADC architecture, introduces a new functional check for measuring alias rejection. The analog input signal frequency to the ADC is swept and the contribution of each out-of-band input signal is calculated by measuring the magnitude of the foldback (if any) of the test frequency tone relative to the tone used.

Figure 11 shows the alias rejection performance of the AD4134 for out-of-band frequencies with a performance bandwidth of 160 kHz and a sampling frequency of 24 MHz. For a frequency of 23.84 MHz (fs _– 160 kHz), the alias rejection is –85 dB, which is the alias rejection specification for the ADC. It can also be seen from the figure that for other intermediate frequencies, the alias rejection is better than –100 dB. For more details on the inherent alias rejection and options to further improve this rejection, see the AD4134 data sheet.

Figure 11. Aliasing rejection vs. out-of-band frequency.

The CTSD ADC concepts we have described in this article help signal chain designers understand the resistive input, resistive reference, and inherent alias rejection characteristics of this architecture. An easy-to-drive input and reference voltage source, as well as the absence of an AAF design in the CTSD ADC signal chain, together create a new simplified ADC front-end design suitable for a variety of applications.