// // module counter(clk,rst_n,led); input clk; //clock signal, 50MHz input rst_n; //reset signal, low effective output led; //LED control, 1---extinguish reg[23:0] cnt; always@(posedge clk or negedge rst_n) if(!rst_n) cnt<=24\'d0; else cnt<=cnt+1\'b1; assign led=cnt[23]; //0--24 is low level endmodule
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