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Design and implementation of a high-speed parallel data acquisition system based on reconfiguration

2013-08-31
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Abstract: This paper introduces a design scheme and implementation method of a high-speed parallel data acquisition system based on reconfigurable technology. Each acquisition channel of the system consists of a group of A/D and dual-end RAM, and multiple acquisition channel modules form a multi-channel full parallel acquisition system; Altera\'s field programmable gate array (FPGA) EP1C6-8 and soft-core CPU are used as the data processing and control core, asynchronous dual-end RAM is used as the data buffer, and the USB controller is CY7C68013. The acquisition system enables data acquisition, data processing, and data transmission to be executed in parallel, and the system has strong fault tolerance. This paper describes the hardware and software implementation of the design scheme, and experiments show that the system has the characteristics of high speed, real-time, low energy consumption, and strong fault tolerance.

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