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Design of a Configurable Cache RAM Memory

  • 2013-09-19
  • 149.36KB
  • Points it Requires : 2

Different applications have different requirements for memory structures: when running control tasks, cache matching speed differences are required; when processing data streams, on-chip memory is required to increase access bandwidth. This paper designs a configurable cache/SRAM memory based on SRAM. Through independent addressing of data memory and full sharing of control and data paths, a four-way group-connected cache with a capacity of 16KB and a SRAM with a capacity of 16KB are realized. Comprehensive results show that compared with ordinary cache, the design only increases the delay by 0.035% and the number of gates by 1.06%.

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