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Design of High-Speed ​​Digital Correlator Based on FPGA

  • 2013-09-16
  • 114.84KB
  • Points it Requires : 2

In the data transmission process of digital communication, it is necessary to keep the data synchronized during the transmission process. Therefore, frame synchronization words should be inserted for detection during the data transmission process to effectively avoid the asynchronous problem of sending and receiving data during the transmission process. This paper proposes a method of designing a high-speed digital correlator based on FPGA using pipeline technology. The simulation results show that the design scheme is feasible.

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