Abstract: The design of driving timing circuit is the key technology of CCD application. Based on the analysis of the driving timing relationship of ATMEL\'s TH7834C long-line array CCD device, the driving timing circuit of TH7834C is designed. Field programmable gate array (FPGA) is selected as the hardware design platform, and the driving timing circuit is described in hardware using VHDL language. The designed driving timing is simulated by EDA software and adapted to ALTERA\'s field programmable gate array EPFl0K30RC240-3. The engineering practice results show that the designed driving timing circuit can not only meet the driving requirements of TH7834C CCD, but also has simple structure, low power consumption, low cost, strong anti-interference ability, high practical value, and is suitable for other types of CCD.
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