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Verilog HDL Basics

2013-09-22
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Verilog HDL basics: Hardware description language is the interface between hardware designers and electronic design automation tools. Its main purpose is to write design files and establish simulation models at the behavior level of electronic systems, that is, to use the huge power of computers to simulate or model complex digital logic and then automatically synthesize to generate a digital logic netlist that meets the requirements and can be implemented in the circuit structure. According to the netlist and a device of a certain process, a specific circuit is automatically generated, and then a delay model of this specific circuit under the process conditions is generated. After the simulation is verified to be correct, it is used to manufacture ASIC chips or written into EPLD and FPGA devices.

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