PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words
×
4 bits)
EDE5108AGSE (64M words
×
8 bits)
Description
The EDE5104AGSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words
×
4 bits
×
4 banks.
The EDE5108AGSE is a 512M bits DDR2 SDRAM
organized as 16,777,216 words
×
8 bits
×
4 banks.
They are packaged in 60-ball FBGA (µBGA
) package.
Features
•
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
•
Double-data-rate architecture: two data transfers per
clock cycle
•
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
•
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
•
Four internal banks for concurrent operation
•
Data mask (DM) for write data
•
Burst lengths: 4, 8
•
/CAS Latency (CL): 3, 4, 5
•
Auto precharge operation for each burst access
•
Auto refresh and self refresh modes
•
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
SSTL_18 compatible I/O
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
•
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
•
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
•
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
•
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0715E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2005
EDE5104AGSE, EDE5108AGSE
Ordering Information
Part number
EDE5104AGSE-6C-E
EDE5104AGSE-6E-E
EDE5104AGSE-5C-E
EDE5104AGSE-4A-E
EDE5108AGSE-6C-E
EDE5108AGSE-6E-E
EDE5108AGSE-5C-E
EDE5108AGSE-4A-E
Mask
version
Organization
(words
×
bits)
128M
×
4
Internal
Banks
Speed bin
(CL-tRCD-tRP)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
DDR2-667 (4-4-4)
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR2-400 (3-3-3)
Package
G
4
60-ball FBGA (µBGA)
64M
×
8
Part Number
E D E 51 04 A G SE - 6C - E
Elpida Memory
Type
D: Monolithic Device
Product Family
E: DDR2
Environment code
E: Lead Free
Density / Bank
51: 512Mb /4-bank
Organization
04: x4
08: x8
Power Supply, Interface
A: 1.8V, SSTL_18
Speed
6C: DDR2-667 (4-4-4)
6E: DDR2-667 (5-5-5)
5C: DDR2-533 (4-4-4)
4A: DDR2-400 (3-3-3)
Package
SE: FBGA (µBGA with back cover)
Die Rev.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
2
EDE5104AGSE, EDE5108AGSE
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA (µBGA)
1
A
2
3
7
8
9
VDD
NU/ /RDQS
VSS
B
C
D
(NC)*
(NC)*
VSSQ
/DQS
VDDQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
(Top view)
DQ6
DM/RDQS
(NC)*
VSSQ
(DM)*
VDDQ
DQ4
DQ1
VDDQ
VSSQ
DQ3
VSS
/WE
BA1
A1
A5
A9
NC
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
(NC)*
DQ7
VDDQ
(NC)*
DQ5
E
VDDL
VREF
F
VDD
ODT
CKE
G
NC
H
BA0
A10
VDD
J
VSS
K
L
A3
A7
VSS
VDD
A12
Note: ( )* marked pins are for
×4
organization.
Pin name
A0 to A13
BA0, BA1
DQ0 to DQ15
DQS, /DQS
RDQS, /RDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Differential data strobe for read
Chip select
Command input
Clock enable
Differential clock input
Write data mask
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*
NU*
1
2
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
3
EDE5104AGSE, EDE5108AGSE
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Specifications.................................................................................................................................5
Block Diagram .............................................................................................................................................15
Pin Function.................................................................................................................................................16
Command Operation ...................................................................................................................................18
Simplified State Diagram .............................................................................................................................25
Operation of DDR2 SDRAM ........................................................................................................................26
Package Drawing ........................................................................................................................................62
Recommended Soldering Conditions..........................................................................................................63
Preliminary Data Sheet E0715E20 (Ver. 2.0)
4
EDE5104AGSE, EDE5108AGSE
Electrical Specifications
•
All voltages are referenced to VSS (GND)
•
Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage for output
Input voltage
Output voltage
Storage temperature
Power dissipation
Short circuit output current
Symbol
VDD
VDDQ
VIN
VOUT
Tstg
PD
IOUT
Rating
−1.0
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−0.5
to +2.3
−55
to +100
1.0
50
Unit
V
V
V
V
°C
W
mA
Notes
1
1
1
1
1, 2
1
1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter
Operating case temperature
Symbol
TC
Rating
0 to +95
Unit
°C
Notes
1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0°C to +85°C with full AC and DC specifications.
Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature Self-Refresh entry via A7 "1" on
EMRS (2).
Preliminary Data Sheet E0715E20 (Ver. 2.0)
5
京公网安备 11010802033920号
EEWORLD
