CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
E
e-max
V
DD
I
DD
I
DD1
f
OSC
1
f
OSC
2
f
I2C
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
V
REF
V
TL
V
TH
I
SDA
I
INT
NOTES:
V
DD
= 3V, T
A
= +25°C, R
EXT
= 100kΩ, unless otherwise specified. Internal Timing Mode operation (See
“Principles of Operation” on page 3).
CONDITION
@ Gain/Range = 4, and R
EXT
= 25kΩ
2.5
0.25
Software disabled
Gain/Range = 1 or 2
Gain/Range = 3 or 4
308
616
0.1
342
684
1 to 400
E = 0 lux, Gain/Range = 1
0
32767
E = 300 lux, fluorescent light, Gain/Range = 1
(Note 2)
E = 300 lux, fluorescent light, Gain/Range = 2
(Note 2)
E = 300 lux, fluorescent light, Gain/Range = 3
(Note 2)
E = 300 lux, fluorescent light, Gain/Range = 4
(Note 2)
0.490
(Note 3)
(Note 3)
3
3
3300
4400
1100
275
69
0.515
1.05
1.95
5
5
0.540
5500
6
MIN
TYP
128k
3.30
0.33
1
377
754
MAX
UNIT
lux
V
mA
µA
kHz
kHz
kHz
Counts
Counts
Counts
Counts
Counts
Counts
V
V
V
mA
mA
DESCRIPTION
Maximum Detectable Light Intensity
Power Supply Range
Supply Current
Supply Current Disabled
Internal Oscillator Frequency
Internal Oscillator Frequency
I
2
C Clock Rate
Dark ADC Code
Full Scale ADC Code
Light Count Output
Light Count Output
Light Count Output
Light Count Output
Voltage of R
EXT
Pin
SCL and SDA Threshold LO
SCL and SDA Threshold HI
SDA Current Sinking Capability
INT Current Sinking Capability
2. Fluorescent light is substituted by a green LED during production.
3. The voltage threshold levels of the SDA and SCL pins are VDD dependent: V
TL
= 0.35*V
DD
. V
TH
= 0.65*V
DD
.
2
FN6476.1
December 10, 2008
ISL29012
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
PIN NAME
VDD
GND
REXT
INT
SCL
SDA
DESCRIPTION
Positive supply; connect this pin to a regulated 2.5V to 3.3V supply.
Ground pin. The thermal pad is connected to the GND pin.
External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor with
1% tolerance.
Interrupt pin; LO for interrupt/alarming, open drain output.
I
2
C serial clock
I
2
C serial data
The I
2
C bus lines can be pulled above VDD, 5.5V max.
Principles of Operation
Photodiodes
The ISL29012 contains two photodiode arrays which convert
light into current. One diode (D1) is sensitive to both visible
and infrared light, while the other one (D2) is only sensitive to
infrared light; see Figure 21. Using the infrared portion of the
light as a baseline, the visible light can be extracted. The
ambient light output is the difference between D1 and D2. The
resultant ALS spectral response vs wavelength is shown in
Figure 7 in the “Typical Performance Curves” on page 11.
After light is converted to current during the light data process,
the current output is converted to digital by a single built-in
integrating type signed 15-bit Analog-to-Digital Converter
(ADC). An I
2
C command reads the visible light intensity in
counts.
The converter is a charge-balancing integrating type signed
15-bit ADC. The chosen method for conversion is best for
converting small current signals in the presence of an AC
periodic noise. A 100ms integration time, for instance, highly
rejects 50Hz and 60Hz power line noise simultaneously. See
“Integration Time or Conversion Time” on page 7 and “Noise
Rejection” on page 8.
The built-in ADC offers user flexibility in integration time or
conversion time. There are two timing modes: Internal Timing
Mode and External Timing Mode. In Internal Timing Mode,
integration time is determined by an internal dual speed
oscillator (f
OSC
), and the n-bit (n = 4, 8, 12,16) counter inside
the ADC. In External Timing Mode, integration time is
determined by the time between two consecutive I
2
C External
Timing Mode commands. See “External Timing Mode” on
page 7. A good balancing act of integration time and resolution
depending on the application is required for optimal results.
The ADC has four I
2
C programmable range selects to
dynamically accommodate various lighting conditions. For
very dim conditions, the ADC can be configured at its lowest
range. For very bright conditions, the ADC can be configured
at its highest range.
Interrupt Function
The active low interrupt pin is an open drain pull-down
configuration. The interrupt pin serves as an alarm or
monitoring function to determine whether the ambient light
exceeds the upper threshold or goes below the lower
threshold. The user can also configure the persistency of the
interrupt pin. This helps to avoid false triggers, such as noise
or sudden spikes in ambient light conditions. An unexpected
camera flash, for example, can be ignored by setting the
persistency to 8 integration cycles.
I
2
C Interface
There are eight (8) 8-bit registers available inside the ISL29012.
The command and control registers define the operation of the
device. The command and control registers do not change until
the registers are overwritten. There are two 8-bit registers that
set the high and low interrupt thresholds. There are four 8-bit
data Read Only registers. Two bytes for the sensor reading and
another two bytes for the timer counts. The data registers
contain the ADC's latest digital output, and the number of clock
cycles in the previous integration period.
The ISL29012’s I
2
C interface slave address is hardwired
internally as 1000100. When 1000100x with x as R or W is
sent after a START condition, this device compares the first
7 bits of this byte to its address and matches.
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. Figure 3 shows a sync_I
2
C timing
diagram sample for externally controlled integration time.
The I
2
C bus master always drives the SCL (clock) line, while
either the master or the slave can drive the SDA (data) line.
Figure 2 shows a sample write. Every I
2
C transaction begins
with the master asserting a start condition (SDA falling while
SCL remains high). The following byte is driven by the
master, and includes the slave address and read/write bit.
The receiving device is responsible for pulling SDA low
during the acknowledgement period.
Every I
2
C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
For more information about the I
2
C standard, please consult
the Phillips
™
I
2
C specification documents.
3
FN6476.1
December 10, 2008
ISL29012
I
2
C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
STOP
START
DEVICE ADDRESS
A
DATA BYTE0
A
STOP
I
2
C SDA
In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
A6
A5
A4
A3
A2
A1
A0
W
A
SDA DRIVEN BY ISL29003
ISL29012
NAK
I
2
C SDA
Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
D7
D6
D5
D4
D3
D2
D1
D0
A
I
2
C CLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 1. I
2
C READ TIMING DIAGRAM SAMPLE
I
2
C DATA
Start
DEVICE ADDRESS
W
A
REGISTER ADDRESS
A
FUNCTIONS
A
STOP
I
2
C SDA In
A6 A5 A4 A3 A2 A1 A0
W
A
R7 R6 R5 R4 R3 R2 R1 R0
A
B7 B6 B5 B4 B3 B2 B1 B0
A
I
2
C SDA Out
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
I
2
C CLK In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 2. I
2
C WRITE TIMING DIAGRAM SAMPLE
I
2
C D A T A
S t a rt
D E V IC E A D D R E S S
W
A
R E G IS T E R A D D R E S S
A S to p
I
2
C S D A In
A6
A5
A4
A3
A2
A1
A0
W
A
R7
R6
R5
R4
R3
R2
R1
R0
A
I
2
C S D A O u t
S D A D R IV EN B Y M A S T ER
A
S D A D R IV EN B Y M A S T ER
A
I
2
C C L K In
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FIGURE 3. I
2
C SYNC_I
2
C TIMING DIAGRAM SAMPLE
4
FN6476.1
December 10, 2008
ISL29012
Register Set
There are eight registers that are available in the ISL29012. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET
BIT
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
REG NAME
COMMAND
CONTROL
Interrupt
Threshold_HI
7
ADCE
0
ITH_HI7
6
ADCPD
0
ITH_HI6
ITH_LO6
S6
S14
T6
T14
5
TIMM
INT_FLAG
ITH_HI5
ITH_LO5
S5
S13
T5
T13
4
0
0
ITH_HI4
ITH_LO4
S4
S12
T4
T12
3
ADCM1
GAIN1
ITH_HI3
ITH_LO3
S3
S11
T3
T11
2
ADCM0
GAIN0
ITH_HI2
ITH_LO2
S2
S10
T2
T10
1
RES1
IC1
ITH_HI1
ITH_LO1
S1
S9
T1
T9
0
RES0
IC0
ITH_HI0
ITH_LO0
S0
S8
T0
T8
DEFAULT
00h
00h
FFh
00h
00h
00h
00h
00h
Interrupt
ITH_LO7
Threshold_LO
LSB SENSOR
MSB
SENSOR
LSB TIMER
MSB TIMER
S7
S15
T7
T15
TABLE 2. WRITE ONLY REGISTERS
ADDRESS
b1xxx_xxxx
REGISTER
NAME
sync_I
2
C
FUNCTIONS/
DESCRIPTION
Writing a logic 1 to this address bit ends the
current ADC-integration and starts another.
Used only with External Timing Mode.
Writing a logic 1 to this address bit clears
the interrupt.
BIT 5
0
1
TABLE 5. TIMING MODE
OPERATION
Internal Timing Mode. Integration time is internally timed
determined by f
OSC
, R
EXT
, and number of clock cycles.
External Timing Mode. Integration time is externally
timed by the I
2
C host.
bx1xx_xxxx
clar_int
Command Register 00(hex)
The Read/Write command register has five functions:
1. Enable; Bit 7. This function either resets the ADC or enables
the ADC in normal operation. A logic 0 disables ADC to
reset-mode. A logic 1 enables ADC to normal operation.
TABLE 3. ENABLE
BIT 7
0
1
OPERATION
Disable ADC-core to reset-mode (default)
Enable ADC-core to normal operation
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and
Bit 2 to 1 and 0 enables ADC to give light count DATA
output.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BITS 3:2
0:0
0:1
1:0
1:1
Disable ADC
Disable ADC
Light count DATA output in signed (n-1) bit *
No operation.
MODE
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
5. Width; Bits 1 and 0. This function determines the number
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device. It also changes the integration time, which is
the period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
measurement.
.
2. ADCPD; Bit 6. This function puts the device in a
power-down mode. A logic 0 puts the device in normal
operation. A logic 1 powers down the device.
TABLE 4. ADCPD
BIT 6
0
1
OPERATION
Normal operation (default)
Power Down
TABLE 7. WIDTH
BITS 1:0
0:0
0:1
1:0
1:1
NUMBER OF CLOCK CYCLES
2
16
= 65,536
2
12
= 4,096
2
8
= 256
2
4
= 16
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an
internal dual speed oscillator (f
OSC
), and the n-bit (n = 4,
8, 12,16) counter inside the ADC. In External Timing
Mode, integration time is determined by the time between
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