2. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
3. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *K
Page 3 of 45
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts - 16-Pin SOIC
Figure 2. 16-pin SOIC (150 Mils) Pinout
[4]
VDD
VSS
Pin Definitions
16-pin SOIC
[4, 5]
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
GP0[3]
CSint
GP0[4]
GP0[0]
GP0[1]
I
2
C
SCL
I
2
C SDA
GP1[0]
GP1[1]
[6]
VSS
GP1[2]
[6]
GP1[3]
GP1[4]
XRES
GP0[2]
VDD
Configurable as CapSense or GPIO
Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved.
Typical range is 1 nF to 4.7 nF.
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
I
2
C clock
I
2
C data
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Ground connection
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Active high external reset with internal pull-down
5. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package
are not available for any functionality.
6. Avoid using GP1[1] and GP1[2] for driving LEDs. These two pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
Document Number: 001-54606 Rev. *K
Page 4 of 45
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
Pinouts - 8-pin SOIC
Figure 3. 8-pin SOIC (150 Mils) pinout
CY8C20142 (4 Button)
Pin Definitions
8-pin SOIC
CY8C20142 (4 Button)
Pin No.
1
2
3
4
5
6
7
8
Name
VSS
I
2
C SCL
I
2
C SDA
GP1[0]
[7]
GP1[1]
[7]
Description
Ground
I
2
C Clock
I
2
C Data
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Configurable as CapSense or GPIO
Supply voltage
GP0[0]
GP0[1]
VDD
Important Note
For information on the preferred dimensions for mounting QFN packages, see the "Application Notes for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at
http://www.amkor.com.
Note
7. Avoid using GP1[0] and GP1[1] for driving LED. These two pins have special functions during power up which is used at factory. LEDs connected to these two pins
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FPGA/CPLD
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