2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL
Fanout Buffer with 2 to 1 Differential Clock Input Mux
Features
•
F
MAX
= 500MHz
• 10 pairs of differential LVPECL outputs
• Low additive jitter, <100fs 12k-20MHz
• Selectable differential input pairs with single ended input
option
• Input CLK accepts: LVPECL, LVDS, CML, SSTL input
level
• Output skew: 35ps (typ)
• Operating Temperature: -40
o
C to 85
o
C
• Core Power supply: 3.3V ±10%, Output Power supply:
2.5V ±5% & 3.3V ±10%
• Packaging (Pb-free & Green):
−32-pin TQFP (FA)
PI6C4853111
Description
The PI6C4853111 is a high-performance low-skew 1-to-10 LVPECL
fanout buffer. The PI6C4853111 features two selectable differential
clock inputs and translates to ten LVPECL outputs. The CLK inputs
accept LVPECL, LVDS, CML and SSTL signals.
PI6C4853111 is ideal for clock distribution applications such as
providing fanout for low noise SaRonix-eCera oscillators.
Block Diagram
Pin Configuration
24 23 22 21 20 19 18 17
V
DDO
25
16
v
DDO
/Q2
26
15
Q7
Q2
27
14
/Q7
31
v
DDO
32
/Q1
Q1
/Q0
Q0
Q3
/Q3
Q4
/Q4
Q5
/Q5
Q6
/Q6
28
29
30
13
12
11
10
1 2 3
CLK_SEL
CLK0
4
/CLK0
5
6
CLK1
7 8
/CLK1
Q8
/Q8
Q9
/Q9
9
v
DDO
PI6C4853111
Rev B
17-0050
1
V
DD
V
EE
March 2017
© Diodes Incorporated
www.diodes.com
NC
PI6C4853111
Pin Description
(1)
Name
V
EE
CLK_SEL
CLK0
/CLK0
CLK1
/CLK1
NC
V
DDO
V
DD
Q3,
/
Q3
Q2,
/
Q2
Q1,
/
Q1
Q0,
/
Q0
Q9,
/
Q9
Q8,
/
Q8
Q7,
/
Q7
Q6,
/
Q6
Q5,
/
Q5
Q4,
/
Q4
Pin #
8
2
3
4
6
7
5
9,16, 25,32
1
24,23
27,26
29,28
31,30
11,10
13,12
15,14
18,17
20,19
22,21
P
P
O
O
O
O
O
O
O
O
O
O
Type
P
I
I
I
I
I
Description
Connect to negative power supply
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input.
LVCMOS/LVTTL level with 50kΩ pull down.
Differential LVPECL clock input with 75kΩ pull-down
Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating.
Differential LVPECL clock input with 75kΩ pull-down
Inverting differential LVPECL clock input. Defaults to VDD/2 if left floating.
No Connect
Output Power pin
Core Power Supply
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Differential output pair, LVPECL interface level.
Note:
1. I = Input, O = Output, P = Power supply connection.
Pin Characteristics
Symbol
R
Parameter
Input Pullup/Pulldown Resistance
Conditions
Min.
Typ.
50
Max.
Units
kΩ
Control Input Function Table
Inputs
0
1
Outputs
CLK0
CLK1
PI6C4853111
Rev B
17-0050
2
www.diodes.com
March 2017
© Diodes Incorporated
PI6C4853111
Absolute Maximum Ratings
(1)
Symbol
V
DD
V
IN
I
OUT
Parameter
Supply voltage
Input voltage
Surge Current
Storage temperature
Smk/source Current, I
BB
Junction Temperature
Conditions
Referenced to GND
Referenced to GND
Min
-0.5
-65
-0.5
Typ
Max
4.6
V
DD
+0.5V
100
150
+0.5
125
Units
V
V
mA
o
C
T
STG
V
BB
T
J
mA
°C
Note:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These ratings are stress specifica-
tions only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Conditions
Symbol
V
DD
V
DDO
T
A
Parameter
Power Supply Voltage
Output Power Supply Voltage
Ambient Temperature
Conditions
Min
3.0
2.375
-40
Typ
Max
3.6
3.6
85
Units
V
V
o
C
LVCMOS/LVTTL DC Characteristics
(T
A
= -40
o
C to +85
o
C, V
DD
= 3.3V ±5%, V
DDO
= 2.5V ±5% to 3.3V ±10%)
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL
CLK_SEL
CLK_SEL
CLK_SEL
V
IN
= V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
-5
Conditions
Min
2
-0.3
Typ
Max
V
DD
+0.3
0.8
150
Units
V
μA
μA
PI6C4853111
Rev B
17-0050
3
www.diodes.com
March 2017
© Diodes Incorporated
PI6C4853111
LVPECL DC Characteristics
(T
A
= -40
o
C to +85
o
C, V
DD
= 3.3V ±10%, V
DDO
= 2.5V ±5% to 3.3V ±10%)
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
I
EE
Input High
Current
Input Low
Current
Parameter
CLK0, CLK1
/CLK0, /CLK1
CLK0, CLK1
/CLK0, /CLK1
Conditions
V
IN
= V
DD
= 3.6V
V
IN
= V
DD
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
-5
-150
0.3
V
EE
+1.5
V
DDO
= 2.5V or 3.3V
V
DDO
= 2.5V or 3.3V
V
DDO
-1.4
V
DDO
-2.0
0.6
@ 400 MHz
120
1
V
DD
V
DDO
-0.9
V
DDO
-1.7
1.0
140
Min
Typ
Max
150
150
Units
µA
µA
µA
µA
V
V
V
V
V
mA
Peak-to-peak Voltage
Common Mode Input Voltage
(1)
Output High Voltage
(2)
Output Low Voltage
(2)
Peak-to-peak Output Voltage Swing
Power Supply Current
Notes:
1. For single-ended applications, the maximum input voltage for CLK and /CLK is V
DD
+0.3V
2. Outputs terminated with 50Ω to V
DD
-2.0V
AC Characteristics
(T
A
= -40
o
C to +85
o
C, V
DD
= 3.3V ±10%, V
DDO
= 2.5V ±5% to 3.3V ±10%)
Symbol
f
max
t
pd
Tsk
t
r
/t
f
odc
J
add
Parameter
Output Frequency
Propagation Delay
(1)
Output-to-output Skew
(2)
Output Rise/Fall time
Output duty cycle
Additive jitter
20% - 80%
f ≤ 400 MHz
V
DD
= V
DDO
= 2.5V or
3.3V
150
45
75
35
Conditions
Min
Typ
Max
500
4
60
700
55
fs
Units
MHz
ns
ps
ps
%
Notes:
1. Measured from the differential input to the differential output crossing point
2 Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point
Additive Jitter Calculation
The additive jitter is measured at 12KHz to 20MHz standard noise band with the LVPECL differential input clock at 156.25MHz.
additive jitter = √ jitter_out
2
- jitter_in
2
Summary of Phase Jitter (Diff. Input and Diff. Output)
Input
V
DD
= 3.3V, 12kHz-20MHz
V
DD
= 2.5V, 12kHz-20MHz
PI6C4853111
Rev B
Output
259.7
201.3
4
Additive Jitter
55.5
75.5
www.diodes.com
Unit
fs RMS
fs RMS
March 2017
© Diodes Incorporated
253.7
186.6
17-0050
PI6C4853111
Packaging Mechanical: 32-pin TQFP (FA)
9.00 BSC
.354
Square
DOCUMENT CONTROL NO.
PD - 1814
REVISION: C
DATE: 03/09/05
Square
7.00
.276
BSC
0.09
0.20
.004
.008
0.25 mm
GAUGE PLANE
0°
7°
1.20
Max.
.047
.004
0.10
Seating Plane
0.45 .018
0.75 .030
1
1.00 REF
.039
0.30 .012
0.45 .018
0.80 BSC
.032
0.05
0.15
.002
.006
0.95
1.05
.037
.041
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335
• www.pericom.com
DESCRIPTION: 32-Pin, Thin Quad Flat Package, TQFP
PACKAGE CODE: FA
Notes:
1. Controlling dimensions in millimeters
2. Ref.: JEDEC MS-026D/ABA
3. Package Outline Exclusive of Mold Flash and Metal Burr
Ordering Information
(1,2,3)
Ordering Code
PI6C4853111FAE
PI6C4853111FAEX
PI6C4853111FAE+CWX
Package Code
FA
FA
FA
Package Description
Pb-free & Green, 32-pin TQFP
Pb-free & Green, 32-pin TQFP, pin 1 orientation on top right
in tape and reel
Pb-free & Green, 32-pin TQFP, pin 1 orientation on top left in
tape and reel
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free & Green
3. X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PI6C4853111
Rev B
17-0050
5
www.diodes.com
March 2017
© Diodes Incorporated
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