Intel
®
82579 Gigabit Ethernet PHY
Datasheet v2.1
Product Features
General
— 10 BASE-T IEEE 802.3 specification
conformance
— 100 BASE-TX IEEE 802.3 specification
conformance
— 1000 BASE-T IEEE 802.3 specification
conformance
— Energy Efficient Ethernet (EEE) IEEE
802.3az support [Low Power Idle (LPI)
mode]
— IEEE 802.3u auto-negotiation conformance
— Supports carrier extension (half duplex)
— Loopback modes for diagnostics
— Advanced digital baseline wander correction
— Automatic MDI/MDIX crossover at all
speeds of operation
— Automatic polarity correction
— MDC/MDIO management interface
— Flexible filters in PHY to reduce integrated
LAN controller power
— Smart speed operation for automatic speed
reduction on faulty cable plants
— PMA loopback capable (no echo cancel)
— 802.1as/1588 conformance
— Intel
®
Stable Image Platform Program
(SIPP)
— iSCSI Boot
— Network proxy/ARP Offload support
Security & Manageability
— Intel
®
vPro support with appropriate Intel
chipset componnets (82579LM SKU)
— MACSec support
1
Performance
— Jumbo Frames (up to 9 kB)
2
— 802.1Q & 802.1p
— Receive Side Scaling (RSS)
— Two Queues (Tx & Rx)
Power
— Flexible power configuration: use either the
PCH 1.05 Vdc or iSVR.
— Reduced power consumption during normal
operation and power down modes
— Integrated Intel
®
Auto Connect Battery
Saver (ACBS)
— Single-pin LAN Disable for easier BIOS
implementation
— Fully integrated Switching Voltage
Regulator (iSVR)
— Low Power LinkUp (LPLU)
MAC/PHY Interconnect
— PCIe-based interface for active state
operation (S0 state)
— SMBus-based interface for host and
management traffic (Sx low power state)
Package/Design
— 48-pin package, 6 x 6 mm with a 0.4 mm
lead pitch and an Exposed Pad* for ground
— Three configurable LED outputs
— Integrated MDI interface termination
resistors to reduce BOM costs
— Reduced BOM cost by sharing SPI flash with
PCH
1. MACSec is not compatible with Intel
®
Active Management Technology
2. Jumbo Frames are not compatible with MACSec.
Reference Number: 324990-007
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82579 GbE PHY may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
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Copyright © 2009-2011, Intel Corporation. All Rights Reserved.
Datasheet — Intel® 82579 Gigabit Ethernet PHY
Contents
1.0
Introduction
.............................................................................................................. 1
1.1
Scope ................................................................................................................ 1
1.2
Overview ........................................................................................................... 1
1.3
Main Flows ......................................................................................................... 2
1.4
References ......................................................................................................... 3
1.5
Product SKUs, Codes, and Device IDs .................................................................... 3
1.6
Supported Operating Systems............................................................................... 4
Interconnects
............................................................................................................ 7
2.1
Introduction ....................................................................................................... 7
2.2
PCIe-Based ........................................................................................................ 7
2.3
SMBus ............................................................................................................... 8
2.4
Transitions between SMBus and PCIe interfaces ...................................................... 9
2.5
Intel
®
6 Series Express Chipset/82579 – SMBus/PCIe Interconnects ........................ 10
Pin Interface
........................................................................................................... 13
3.1
Pin Assignment ................................................................................................. 13
Package...................................................................................................................
17
4.1
Package Type and Mechanical ............................................................................. 17
4.2
Package Electrical and Thermal Characteristics ...................................................... 18
4.3
Power and Ground Requirements......................................................................... 18
4.4
Ball Mapping..................................................................................................... 19
Initialization............................................................................................................
23
5.1
Power Up ......................................................................................................... 23
5.2
Reset Operation ................................................................................................ 24
5.3
Timing Parameters ............................................................................................ 25
Power Management and Delivery.............................................................................
27
6.1
Power Delivery.................................................................................................. 28
6.2
Power Management ........................................................................................... 28
Device Functionality
................................................................................................ 35
7.1
Tx Flow ............................................................................................................ 35
7.2
Rx Flow............................................................................................................ 35
7.3
Flow Control ..................................................................................................... 36
7.4
Wake Up .......................................................................................................... 38
7.5
Network Proxy Functionality................................................................................ 46
7.6
Loopback ......................................................................................................... 52
Electrical and Timing Specifications.........................................................................
53
8.1
Introduction ..................................................................................................... 53
8.2
Operating Conditions ......................................................................................... 53
8.3
Power Delivery.................................................................................................. 54
8.4
I/O DC Parameter ............................................................................................. 56
8.5
Discrete/Integrated Magnetics Specifications......................................................... 60
8.6
Mechanical ...................................................................................................... 60
8.7
Oscillator/Crystal Specifications........................................................................... 60
Programmer’s Visible State
..................................................................................... 63
9.1
Terminology ..................................................................................................... 63
9.2
MDIO Access .................................................................................................... 64
9.3
Addressing ....................................................................................................... 64
9.4
Address Map..................................................................................................... 65
9.5
PHY Registers (Page 0) ...................................................................................... 67
9.6
Port Control Registers (Page 769)........................................................................ 88
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
iii
Intel® 82579 Gigabit Ethernet PHY — Datasheet
9.7
9.8
9.9
9.10
9.11
Statistics Registers ............................................................................................89
PCIe Registers...................................................................................................91
General Registers ..............................................................................................94
Wake Up Registers.............................................................................................97
LPI MMD PHY Registers..................................................................................... 107
10.0 Non-Volatile Memory (NVM)
.................................................................................. 109
10.1 Introduction .................................................................................................... 109
10.2 NVM Programming Procedure Overview .............................................................. 109
10.3 LAN NVM Format and Contents .......................................................................... 111
11.0 Time Synch (IEEE1588 and 802.1AS)
..................................................................... 129
11.1 Overview ........................................................................................................ 129
12.0 Intel
®
6 Series Express Chipset MAC Programming Interface.................................
137
13.0 Reference Schematics
............................................................................................ 225
14.0 Schematic and Board Layout Checklists
................................................................. 227
15.0 Models
................................................................................................................... 229
16
Design Considerations and Guidelines (Non-Mobile Designs)
................................. 232
16.1 PHY Overview.................................................................................................. 233
16.2 Platform LAN Design Guidelines ......................................................................... 236
16.3 PCH – SMBus/PCIe LOM Design Guidelines .......................................................... 244
16.4 SMBus Design Considerations ............................................................................ 245
16.5 General Layout Guidelines................................................................................. 246
16.6 Layout Considerations ...................................................................................... 246
16.7 Guidelines for Component Placement.................................................................. 246
16.8 MDI Differential-Pair Trace Routing for LAN Design ............................................... 249
16.9 Signal Trace Geometry ..................................................................................... 249
16.10 Trace Length and Symmetry ............................................................................. 252
16.11 Impedance Discontinuities ................................................................................ 253
16.12 Reducing Circuit Inductance .............................................................................. 253
16.13 Signal Isolation ............................................................................................... 253
16.14 Power and Ground Planes ................................................................................. 254
16.15 Traces for Decoupling Capacitors ....................................................................... 256
16.16 Ground Planes under a Magnetics Module............................................................ 256
16.17 Light Emitting Diodes ....................................................................................... 258
16.18 Frequency Control Device Design Considerations.................................................. 258
16.19 Crystals and Oscillators .................................................................................... 259
16.20 Quartz Crystal ................................................................................................. 259
16.21 Fixed Crystal Oscillator ..................................................................................... 259
16.22 Crystal Selection Parameters ............................................................................. 260
16.23 Vibrational Mode.............................................................................................. 260
16.24 Nominal Frequency .......................................................................................... 260
16.25 Frequency Tolerance ........................................................................................ 260
16.26 Temperature Stability and Environmental Requirements........................................ 260
16.27 Calibration Mode.............................................................................................. 261
16.28 Load Capacitance............................................................................................. 261
16.29 Shunt Capacitance ........................................................................................... 262
16.30 Equivalent Series Resistance ............................................................................. 262
16.31 Drive Level ..................................................................................................... 262
16.32 Aging ............................................................................................................. 262
16.33 Reference Crystal ............................................................................................ 262
16.34 Oscillator Support ............................................................................................ 264
16.35 Oscillator Placement and Layout Recommendations .............................................. 264
iv
Datasheet — Intel® 82579 Gigabit Ethernet PHY
16.36 Troubleshooting Common Physical Layout Issues ................................................. 265
16.37 Power Delivery................................................................................................ 266
16.38 82579 Power Sequencing ................................................................................. 267
17
Design Considerations and Guidelines (Mobile Designs)
........................................ 268
17.1 PHY Overview ................................................................................................. 269
17.2 Platform LAN Design Guidelines......................................................................... 272
17.3 PCH – SMBus/PCIe LOM Design Guidelines.......................................................... 281
17.4 SMBus Design Considerations ........................................................................... 282
17.5 General Layout Guidelines ................................................................................ 283
17.6 Layout Considerations...................................................................................... 283
17.7 Guidelines for Component Placement ................................................................. 283
17.8 MDI Differential-Pair Trace Routing for LAN Design .............................................. 286
17.9 Signal Trace Geometry..................................................................................... 286
17.10 Trace Length and Symmetry ............................................................................. 288
17.11 Impedance Discontinuities ................................................................................ 289
17.12 Reducing Circuit Inductance.............................................................................. 289
17.13 Signal Isolation ............................................................................................... 289
17.14 Power and Ground Planes ................................................................................. 290
17.15 Traces for Decoupling Capacitors ....................................................................... 292
17.16 Ground Planes under a Magnetics Module ........................................................... 292
17.17 Light Emitting Diodes....................................................................................... 294
17.18 Considerations for Layout ................................................................................. 294
17.19 Frequency Control Device Design Considerations ................................................. 295
17.20 Crystals and Oscillators .................................................................................... 295
17.21 Quartz Crystal ................................................................................................ 295
17.22 Fixed Crystal Oscillator..................................................................................... 296
17.23 Crystal Selection Parameters ............................................................................ 296
17.24 Vibrational Mode ............................................................................................. 296
17.25 Nominal Frequency .......................................................................................... 296
17.26 Frequency Tolerance........................................................................................ 297
17.27 Temperature Stability and Environmental Requirements ....................................... 297
17.28 Calibration Mode ............................................................................................. 297
17.29 Load Capacitance ............................................................................................ 298
17.30 Shunt Capacitance........................................................................................... 298
17.31 Equivalent Series Resistance............................................................................. 298
17.32 Drive Level ..................................................................................................... 299
17.33 Aging............................................................................................................. 299
17.34 Reference Crystal ............................................................................................ 299
17.35 Oscillator Support............................................................................................ 300
17.36 Oscillator Placement and Layout Recommendations.............................................. 301
17.37 LAN Switch..................................................................................................... 302
17.38 Troubleshooting Common Physical Layout Issues ................................................. 302
17.39 Power Delivery................................................................................................ 303
17.40 Power Sequencing .......................................................................................... 304
v
PCB Design
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