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HYMD512M646DLFP8-J

Description
200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)
File Size327KB,17 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
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HYMD512M646DLFP8-J Overview

200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)

200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)
This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb D ver.
DDR SDRAMs in 60 ball FBGA packages on a 200pin glass-epoxy substrate. This Hynix 512Mb D ver. based unbuffered
SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES
JEDEC Standard 200-pin small outline, dual in-line
memory module (SO-DIMM)
Two ranks 128M x 64 organization
2.6V
±
0.1V VDD and VDDQ Power supply for
DDR400, 2.5V
±
0.2V for DDR333 and below
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
133/166/200MHz
DLL aligns DQ and DQS transition with CK transition
Programmable CAS Latency : DDR266(2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial Presence Detect (SPD) with EEPROM
Built with 512Mb DDR SDRAMs in 60 ball
FBGA packages
All lead-free products (RoHS compliant)
ADDRESS TABLE
Organization
1GB
128M x 64
Ranks
2
SDRAMs
64Mb x 8
# of DRAMs
16
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
Refresh
Method
8K / 64ms
PERFORMANCE RANGE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
CL=3
Max Clock
Frequency
CL=2.5
CL=2
-D43
1
DDR400B
3-3-3
200
166
133
-J
DDR333
2.5-3-3
-
166
133
-H
DDR266B
2.5-3-3
-
133
133
Note:
1. 2.6V
±
0.1V VDD and VDDQ Power supply for DDR400 and 2.5V
±
0.2V for DDR333 and below
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / June 2007
1

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Description 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA) 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA) 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA) 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA) 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA) 200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)
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