HYMD512M646DFP8-D43 datasheet, PDF

200pin DDR SDRAM SO-DIMMs based on 512Mb D ver. (FBGA)

This Hynix unbuffered Small Outline, Dual In-Line Memory Module (DIMM) series consists of 512Mb D ver.

DDR SDRAMs in 60 ball FBGA packages on a 200pin glass-epoxy substrate. This Hynix 512Mb D ver. based unbuffered

SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.

It is suitable for easy interchange and addition.

FEATURES

•

JEDEC Standard 200-pin small outline, dual in-line

memory module (SO-DIMM)

Two ranks 128M x 64 organization

2.6V

±

0.1V VDD and VDDQ Power supply for

DDR400, 2.5V

±

0.2V for DDR333 and below

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

133/166/200MHz

DLL aligns DQ and DQS transition with CK transition

Programmable CAS Latency : DDR266(2.5 clock),

DDR333(2.5 clock), DDR400(3 clock)

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial Presence Detect (SPD) with EEPROM

Built with 512Mb DDR SDRAMs in 60 ball

FBGA packages

All lead-free products (RoHS compliant)

ADDRESS TABLE

Organization

1GB

128M x 64

Ranks

2

SDRAMs

64Mb x 8

# of DRAMs

16

# of row/bank/column Address

13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)

Refresh

Method

8K / 64ms

PERFORMANCE RANGE

Part-Number Suffix

Speed Bin

CL - tRCD- tRP

CL=3

Max Clock

Frequency

CL=2.5

CL=2

-D43

1

DDR400B

3-3-3

200

166

133

-J

DDR333

2.5-3-3

-

166

133

-H

DDR266B

2.5-3-3

-

133

Note:

1. 2.6V

±

0.1V VDD and VDDQ Power supply for DDR400 and 2.5V

±

0.2V for DDR333 and below

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / June 2007

1

11

200pin DDR SDRAM SO-DIMMs

ORDERING INFORMATION

Part Number

HYMD512M646D[L]FP8-D43/J/H

Density

1GB

Organization

128M x 8

# of

DRAMs

16

Material

Lead-free

1

DIMM Dimension

67.60 x 31.75 x 3.8 [mm

3

]

Note:

1. The “Lead-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.

* These Products are built with HY5DU124(8,16)22D[L]FP the Hynix DDR SDRAM component

Rev. 1.0 / June 2007

2

11

200pin DDR SDRAM SO-DIMMs

PIN DESCRIPTION

CK0, /CK0

/CS0, /CS1

CKE0, CKE1

/RAS, /CAS, /WE

A0 ~ A12

BA0, BA1

DQ0~DQ63

CB0~CB7

DQS0~DQS17

DM0~7

VDD

/RESET

Pin Description

Differential Clock Inputs

Chip Select Input

Clock Enable Input

Commend Sets Inputs

Address

Bank Address

Data Inputs/Outputs

Data Strobe Inputs/Outputs

Data-in Mask

Power Supply

Reset Enable

VDDQ

VSS

VREF

VDDSPD

SA0~SA2

SCL

SDA

WP

VDDID

DU

NC

FETEN

Pin Description

DQs Power Supply

Ground

Reference Power Supply

Power Supply for SPD

E

2

PROM Address Inputs

E

2

PROM Clock

E

2

PROM Data I/O

Write Protect Flag

VDD Identification Flag

Do not Use

No Connection

FET Enable

PIN ASSIGNMENT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Name

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

NC

/RESET

VSS

DQ8

DQ9

DQS1

VDDQ

CK1*

/CK1*

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

A9

DQ18

A7

VDDQ

DQ19

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

Name

A5

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

VSS

A1

CB0*

CB1*

VDD

DQS8

A0

CB2*

VSS

CB3*

BA1

Key

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Name

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

/CS2*

DQ48

DQ49

VSS

CK2*

/CK2*

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

NU

SDA

SCL

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Name

VSS

DQ4

DQ5

VDDQ

DM0,DQS9

DQ6

DQ7

VSS

NC

VDDQ

DQ12

DQ13

DM1,DQS10

VDD

DQ14

DQ15

CKE1

VDDQ

BA2*

DQ20

A12

VSS

DQ21

A11

DM2,DQS11

VDD

DQ22

A8

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Name

VSS

A6

DQ28

DQ29

VDDQ

DM3,DQS12

A3

DQ30

VSS

DQ31

CB4*

CB5*

VDDQ

CK0

/CK0

VSS

DM8,DQS17

A10

CB6*

VDDQ

CB7*

key

VSS

DQ36

DQ37

VDD

DM4,DQS13

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Name

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5,DQS14

VSS

DQ46

DQ47

NC

VDDQ

DQ52

DQ53

A13

2

, NC

VDD

DM6

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

DM7,DQS16

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

Note:

1. * : These pins are not used in this module.

2. Pin 167 is NC for 256MB, 512MB, and 1GB, or A13 for 2GB module.

Rev. 1.0 / June 2007

3

11

200pin DDR SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB, 128M x 64 Unbuffered SO-DIMM : HYMD512M646D[L]FP8

/CS1

/CS0

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

BA0-BA1

A0-A12

CKE1

/RAS

/CAS

CKE0

/WE

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

/CS

DQS

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

DM

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

/CS

DQS

D0

I/O3

I/O4

I/O5

I/O6

I/O7

D8

D4

D1

D12

2

D1

D9

D5

D13

D2

D10

D6

D14

D3

D11

D7

D15

BA0-BA1 : SDRAMs D0-D15

A0-A12 : SDRAMs D0-D15

CKE : SDRAMs D8-D15

/RAS : SDRAMs D0-D15

/CAS : SDRAMs D0-D15

CKE : SDRAMs D0-D7

/WE : SDRAMs D0-D15

SCL

WP

A0

A1

A2

VDD SPD

Serial PD

SDA

VDD /VDDQ

SPD

DO-D15

Strap:see Note 4

VREF

VSS

VDDID

SA0 SA1 SA2

Note :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%.

4. VDDID strap connections (for memory device VDD, VDDQ) :

STRAP OUT (OPEN) : VDD = VDDQ

STRAP IN (VSS) : VDD

≠

VDDQ

CK0

/CK0

CK1

/CK1

CK2

/CK2

8 loads

0 loads

Rev. 1.0 / June 2007

4

11

200pin DDR SDRAM SO-DIMMs

ABSOLUTE MAXIMUM RATINGS

1

Parameter

Operating Temperature (Ambient)

Storage Temperature

Voltage on V

DD

relative to V

SS

Voltage on V

DDQ

relative to V

SS

Voltage on inputs relative to Vss

Voltage on I/O pins realtive to Vss

Output Short Circuit Current

Soldering Temperature

⋅

Time

Symbol

T

A

T

STG

V

DD

V

DDQ

V

INPUT

V

IO

IOS

T

SOLDER

Rating

0 ~ 70

-55 ~ 150

-1.0 ~ 3.6

-0.5 ~3.6

50

260

⋅

10

o

Unit

o

C

o

C

V

mA

C

⋅

Sec

Note:

1. Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(TA=0 to 70

o

C, Voltage referenced to V

SS

= 0V)

Parameter

Power Supply Voltage (DDR 200, 266, 333)

Power Supply Voltage (DDR 400)

Power Supply Voltage (DDR 200, 266, 333)

Power Supply Voltage (DDR 400)

Input High Voltage

Input Low Voltage

Termination Voltage

Reference Voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input Leakage Current

Output Leakage Current

Output High Current

Normal Strength

(min VDDQ, min VREF, min VTT)

Output Driver

(V

OUT

=VTT°æ

0.84

) Output Low Current

(min VDDQ, max VREF, max VTT)

Half Strength Out- Output High Current

put Driver

(min VDDQ, min VREF, min VTT)

(V

OUT

=VTT°æ0.68)

Symbol

V

DD

V

DD

V

DDQ

V

DDQ

V

IH

V

IL

V

TT

V

REF

VIN(DC)

VID(DC)

VI(RATIO)

I

LI

I

LO

IOH

IOL

IOH

IOL

Min

2.3

2.5

2.3

2.5

V

REF

+ 0.15

-0.3

V

REF

- 0.04

0.49*VDDQ

-0.3

0.36

0.71

-2

-5

-16.8

16.8

-13.6

13.6

Typ.

2.5

2.6

2.5

2.6

-

V

REF

0.5*VDDQ

-

Max

2.7

V

DDQ

+ 0.3

V

REF

- 0.15

V

REF

+ 0.04

0.51*VDDQ

VDDQ+0.3

VDDQ+0.6

1.4

2

5

-

Unit

V

-

uA

mA

Note

2

1

1,2

3

4

5

6

7

8

Output Low Current

(min VDDQ, max VREF, max VTT)

Notes:

1. V

DDQ

must not exceed the level of V

DD

.

2. For DDR400, VDD=2.6V

±

0.1V, VDDQ=2.6V

±

0.1V

3. V

IL

(min) is acceptable -1.5V AC pulse width with < 5ns of duration.

4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to

peak noise on VREF may not exceed

±

2% of the DC value.

5. VID is the magnitude of the difference between the input level on CK and the input level on /CK.

6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-

ture and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum differ-

ence between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum

pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

7. VIN=0 to VDD, All other pins are not tested under VIN =0V.

8. DQs are disabled, VOUT=0 to VDDQ.

Rev. 1.0 / June 2007

5

HYMD512M646DFP8-D43

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