EDJ2104BASE-8C-F datasheet, PDF

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EDJ2104BASE-8C-F: Description2G bits DDR3 SDRAM; Categorystorage storage; File Size2MB，148 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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EDJ2104BASE-8C-F Overview

2G bits DDR3 SDRAM

EDJ2104BASE-8C-F Parametric

Parameter Name	Attribute value
Maker	ELPIDA
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	78
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78
JESD-609 code	e1
length	11 mm
memory density	2147483648 bi
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	78
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	9 mm

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PRELIMINARY DATA SHEET

2G bits DDR3 SDRAM

EDJ2104BASE (512M words

4 bits)

EDJ2108BASE (256M words

8 bits)

Specifications

•

Density: 2G bits

•

Organization



64M words

4 bits

8 banks (EDJ2104BASE)



32M words

8 bits

8 banks (EDJ2108BASE)

•

Package



78-ball FBGA



Lead-free (RoHS compliant) and Halogen-free

•

Power supply: VDD, VDDQ

1.5V

0.075V

•

Data rate



1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)

•

1KB page size



Row address: A0 to A14



Column address: A0 to A9, A11 (EDJ2104BASE)

A0 to A9 (EDJ2108BASE)

•

Eight internal banks for concurrent operation

•

Interface: SSTL_15

•

Burst lengths (BL): 8 and 4 with Burst Chop (BC)

•

Burst type (BT):



Sequential (8, 4 with BC)



Interleave (8, 4 with BC)

•

/CAS Latency (CL): 6, 7, 8, 9, 10, 11

•

/CAS Write Latency (CWL): 5, 6, 7, 8

•

Precharge: auto precharge option for each burst

access

•

Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

•

Refresh: auto-refresh, self-refresh

•

Refresh cycles



Average refresh period

7.8µs at 0°C

≤

≤ +85°C

3.9µs at

+85°C <

≤ +95°C

•

Operating case temperature range



TC = 0°C to +95°C

Features

•

Double-data-rate architecture; two data transfers per

clock cycle

•

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

•

Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

•

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

•

Differential clock inputs (CK and /CK)

•

DLL aligns DQ and DQS transitions with CK

transitions

•

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

•

Data mask (DM) for write data

•

Posted /CAS by programmable additive latency for

better command and data bus efficiency

•

On-Die Termination (ODT) for better signal quality



Synchronous ODT



Dynamic ODT



Asynchronous ODT

•

Multi Purpose Register (MPR) for temperature read

out

•

ZQ calibration for DQ drive and ODT

•

Programmable Partial Array Self-Refresh (PASR)

•

/RESET pin for Power-up sequence and reset

function

•

SRT range:



Normal/extended

•

Programmable Output driver impedance control

Document No. E1505E20 (Ver. 2.0)

Date Published November 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida

Memory, Inc. 2009

EDJ2104BASE, EDJ2108BASE

CONTENTS

Specifications.................................................................................................................................................1

Features.........................................................................................................................................................1

Ordering Information......................................................................................................................................2

Part Number ..................................................................................................................................................2

Pin Configurations .........................................................................................................................................3

Electrical Conditions ......................................................................................................................................6

Absolute Maximum Ratings .........................................................................................................................6

Operating Temperature Condition ...............................................................................................................6

Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ..................7

AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V)......................7

VREF Tolerances ........................................................................................................................................8

Input Slew Rate Derating .............................................................................................................................9

AC and DC Logic Input Levels for Differential Signals ............................................................................... 15

AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................. 20

AC Overshoot/Undershoot Specification.................................................................................................... 22

Output Driver Impedance........................................................................................................................... 23

On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................25

ODT Timing Definitions.............................................................................................................................. 27

IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) .................................. 31

Electrical Specifications...............................................................................................................................44

DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V) ................................................ 44

Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V

0.075V) .................................................................... 46

Standard Speed Bins ................................................................................................................................. 47

AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V

0.075V, VSS, VSSQ = 0V)...................... 51

Block Diagram .............................................................................................................................................65

Pin Function.................................................................................................................................................66

Command Operation ...................................................................................................................................68

Command Truth Table ............................................................................................................................... 68

CKE Truth Table ........................................................................................................................................ 72

Simplified State Diagram .............................................................................................................................73

RESET and Initialization Procedure ............................................................................................................74

Power-Up and Initialization Sequence ....................................................................................................... 74

Reset and Initialization with Stable Power ................................................................................................. 75

Programming the Mode Register.................................................................................................................76

Mode Register Set Command Cycle Time (tMRD) ....................................................................................76

MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 76

DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 77

DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 78

DDR3 SDRAM Mode Register 2 [MR2] ..................................................................................................... 79

Preliminary Data Sheet E1505E20 (Ver. 2.0)

EDJ2104BASE, EDJ2108BASE

DDR3 SDRAM Mode Register 3 [MR3] ..................................................................................................... 80

Burst Length (MR0) ................................................................................................................................... 81

Burst Type (MR0) ...................................................................................................................................... 81

DLL Enable (MR1) ..................................................................................................................................... 82

DLL-off Mode ............................................................................................................................................. 82

DLL on/off switching procedure ................................................................................................................. 83

Additive Latency (MR1).............................................................................................................................. 85

Write Leveling (MR1) ................................................................................................................................. 86

TDQS, /TDQS function (MR1) ................................................................................................................... 89

Extended Temperature Usage (MR2) ........................................................................................................ 90

Multi Purpose Register (MR3).................................................................................................................... 92

Operation of the DDR3 SDRAM ..................................................................................................................99

Read Timing Definition............................................................................................................................... 99

Read Operation ....................................................................................................................................... 103

Write Timing Definition............................................................................................................................. 110

Write Operation........................................................................................................................................ 111

Write Timing Violations ............................................................................................................................ 117

Write Data Mask ...................................................................................................................................... 118

Precharge ................................................................................................................................................ 119

Auto Precharge Operation ....................................................................................................................... 120

Auto-Refresh............................................................................................................................................ 121

Self-Refresh............................................................................................................................................. 122

Power-Down Mode .................................................................................................................................. 123

Input Clock Frequency Change during Precharge Power-Down.............................................................. 130

On-Die Termination (ODT)....................................................................................................................... 131

ZQ Calibration.......................................................................................................................................... 143

Package Drawing ......................................................................................................................................145

Recommended Soldering Conditions........................................................................................................146

Preliminary Data Sheet E1505E20 (Ver. 2.0)

EDJ2104BASE-8C-F Related Products

	EDJ2104BASE-8C-F	EDJ2104BASE	EDJ2104BASE-AE-F	EDJ2104BASE-DJ-F	EDJ2104BASE-GN-F	EDJ2108BASE-AE-F	EDJ2108BASE-DJ-F	EDJ2108BASE-GN-F
Description	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM	2G bits DDR3 SDRAM
Maker	ELPIDA	-	ELPIDA	ELPIDA	ELPIDA	ELPIDA	ELPIDA	ELPIDA
Parts packaging code	BGA	-	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	TFBGA,	-	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Contacts	78	-	78	78	78	78	78	78
Reach Compliance Code	unknow	-	unknow	unknow	unknown	unknow	unknow	unknown
ECCN code	EAR99	-	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	-	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78	-	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78
JESD-609 code	e1	-	e1	e1	e1	e1	e1	e1
length	11 mm	-	11 mm	11 mm	11 mm	11 mm	11 mm	11 mm
memory density	2147483648 bi	-	2147483648 bi	2147483648 bi	2147483648 bit	2147483648 bi	2147483648 bi	2147483648 bit
Memory IC Type	DDR DRAM	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	4	-	4	4	4	8	8	8
Number of functions	1	-	1	1	1	1	1	1
Number of ports	1	-	1	1	1	1	1	1
Number of terminals	78	-	78	78	78	78	78	78
word count	536870912 words	-	536870912 words	536870912 words	536870912 words	268435456 words	268435456 words	268435456 words
character code	512000000	-	512000000	512000000	512000000	256000000	256000000	256000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	-	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	512MX4	-	512MX4	512MX4	512MX4	256MX8	256MX8	256MX8
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	-	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	-	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.575 V	-	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage (Vsup)	1.425 V	-	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage (Vsup)	1.5 V	-	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	-	YES	YES	YES	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	-	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	TIN SILVER COPPER	-	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	-	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	-	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	9 mm	-	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm

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