SN74LS280
9-Bit Odd/Even Parity
Generators/Checkers
The SN74LS280 is a Universal 9-Bit Parity Generator / Checker. It
features odd / even outputs to facilitate either odd or even parity. By
cascading, the word length is easily expanded.
The LS280 is designed without the expander input implementation,
but the corresponding function is provided by an input at Pin 4 and the
absence of any connection at Pin 3. This design permits the LS280 to
be substituted for the LS180 which results in improved performance.
The LS280 has buffered inputs to lower the drive requirements to one
LS unit load.
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LOW
POWER
SCHOTTKY
•
•
•
•
•
Generates Either Odd or Even Parity for Nine Data Lines
Typical Data-to-Output Delay of only 33 ns
Cascadable for n-Bits
Can Be Used To Upgrade Systems Using MSI Parity Circuits
Typical Power Dissipation = 80 mW
14
1
INPUTS
V
CC
14
F
13
F
G
H
1
G
2
H
3
NC
I
E
12
E
D
11
D
C
10
C
B
9
B
A
8
PLASTIC
N SUFFIX
CASE 646
A
∑
∑
EVEN ODD
14
1
4
5
6
7
I
∑
∑
GND
INPUT EVEN ODD
OUTPUTS
INPUTS
SOIC
D SUFFIX
CASE 751A
FUNCTION TABLE
NUMBER OF INPUTS A
THRU 1 THAT ARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H = HIGH Level, L = LOW Level
OUTPUTS
∑EVEN
H
L
∑ODD
L
H
ORDERING INFORMATION
Device
SN74LS280N
Package
14 Pin DIP
14 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
SN74LS280D
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS280/D
SN74LS280
FUNCTIONAL BLOCK DIAGRAM
A (8)
B
(9)
(5)
∑
EVEN
C (10)
D
E
F
(11)
(12)
(13)
(6)
∑
ODD
G
H
(1)
(2)
I (4)
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
27
0.5
20
V
µA
mA
mA
mA
mA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation Delay, Data to Output
ΣEVEN
Propagation Delay, Data to Output
ΣODD
Min
Typ
33
29
23
31
Max
50
45
35
50
Unit
ns
C
L
= 15 pF
ns
Test Conditions
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2
SN74LS280
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M
14
8
B
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
–––
10
_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
–––
10
_
0.38
1.01
A
F
N
–T–
SEATING
PLANE
L
C
K
H
G
D
14 PL
0.13 (0.005)
M
J
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
–A–
14
8
–B–
1
7
P
7 PL
0.25 (0.010)
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.228
0.244
0.010
0.019
G
C
R
X 45
_
F
–T–
SEATING
PLANE
D
14 PL
0.25 (0.010)
K
M
M
S
J
T B
A
S
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3
SN74LS280
ON Semiconductor
and
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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