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SN74LS280DR2

Description
LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOIC-14
Categorylogic   
File Size106KB,4 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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SN74LS280DR2 Overview

LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOIC-14

SN74LS280DR2 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerON Semiconductor
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codenot_compliant
Other featuresODD/EVEN PARITY GENERATOR
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.65 mm
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)50 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
SN74LS280
9-Bit Odd/Even Parity
Generators/Checkers
The SN74LS280 is a Universal 9-Bit Parity Generator / Checker. It
features odd / even outputs to facilitate either odd or even parity. By
cascading, the word length is easily expanded.
The LS280 is designed without the expander input implementation,
but the corresponding function is provided by an input at Pin 4 and the
absence of any connection at Pin 3. This design permits the LS280 to
be substituted for the LS180 which results in improved performance.
The LS280 has buffered inputs to lower the drive requirements to one
LS unit load.
http://onsemi.com
LOW
POWER
SCHOTTKY
Generates Either Odd or Even Parity for Nine Data Lines
Typical Data-to-Output Delay of only 33 ns
Cascadable for n-Bits
Can Be Used To Upgrade Systems Using MSI Parity Circuits
Typical Power Dissipation = 80 mW
14
1
INPUTS
V
CC
14
F
13
F
G
H
1
G
2
H
3
NC
I
E
12
E
D
11
D
C
10
C
B
9
B
A
8
PLASTIC
N SUFFIX
CASE 646
A
EVEN ODD
14
1
4
5
6
7
I
GND
INPUT EVEN ODD
OUTPUTS
INPUTS
SOIC
D SUFFIX
CASE 751A
FUNCTION TABLE
NUMBER OF INPUTS A
THRU 1 THAT ARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H = HIGH Level, L = LOW Level
OUTPUTS
∑EVEN
H
L
∑ODD
L
H
ORDERING INFORMATION
Device
SN74LS280N
Package
14 Pin DIP
14 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
SN74LS280D
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS280/D

SN74LS280DR2 Related Products

SN74LS280DR2 SN74LS280M SN74LS280MEL SN74LS280ML2 SN74LS280MR2 SN74LS280ML1
Description LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, SOIC-14 LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SOP-14 IC LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SOP-14, Arithmetic Circuit SN74LS280ML2 SN74LS280MR2 SN74LS280ML1
Reach Compliance Code not_compliant unknown not_compliant unknown unknown unknown
Maker ON Semiconductor - ON Semiconductor ON Semiconductor ON Semiconductor ON Semiconductor

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