AD7840BQ datasheet, PDF - EEWORLD Datasheet

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AD7840BQ: DescriptionIC SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24, HERMETIC SEALED, CERDIP-24, Digital to Analog Converter; CategoryAnalog mixed-signal IC converter; File Size335KB，16 Pages; ManufacturerADI; Websitehttps://www.analog.com

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AD7840BQ Overview

IC SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24, HERMETIC SEALED, CERDIP-24, Digital to Analog Converter

AD7840BQ Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	ADI
Parts packaging code	DIP
package instruction	HERMETIC SEALED, CERDIP-24
Contacts	24
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum analog output voltage	3 V
Minimum analog output voltage	-3 V
Converter type	D/A CONVERTER
Enter bit code	2\'S COMPLEMENT BINARY
Input format	SERIAL, PARALLEL, WORD
JESD-30 code	R-GDIP-T24
JESD-609 code	e0
Maximum linear error (EL)	0.0061%
Nominal negative supply voltage	-5 V
Number of digits	14
Number of functions	1
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	+-5 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum stabilization time	4 µs
Nominal settling time (tstl)	2.5 µs
Maximum slew rate	14 mA
Nominal supply voltage	5 V
surface mount	NO
technology	BICMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

AD7840BQ Preview

FEATURES

Complete 14-Bit Voltage Output DAC

Parallel and Serial Interface Capability

80 dB Signal-to-Noise Ratio

Interfaces to High Speed DSP Processors

e.g., ADSP-2100, TMS32010, TMS32020

45 ns min

Pulse Width

Low Power – 70 mW typ.

Operates from 5 V Supplies

LC MOS

Complete 14-Bit DAC

AD7840

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7840 is a fast, complete 14-bit voltage output D/A con-

verter. It consists of a 14-bit DAC, 3 V buried Zener reference,

DAC output amplifier and high speed control logic.

The part features double-buffered interface logic with a 14-bit

input latch and 14-bit DAC latch. Data is loaded to the input

latch in either of two modes, parallel or serial. This data is then

transferred to the DAC latch under control of an asynchronous

LDAC

signal. A fast data setup time of 21 ns allows direct

parallel interfacing to digital signal processors and high speed

16-bit microprocessors. In the serial mode, the maximum serial

data clock rate can be as high as 6 MHz.

The analog output from the AD7840 provides a bipolar output

range of

3 V. The AD7840 is fully specified for dynamic per-

formance parameters such as signal-to-noise ratio and harmonic

distortion as well as for traditional dc specifications. Full power

output signals up to 20 kHz can be created.

The AD7840 is fabricated in linear compatible CMOS

(LC

MOS), an advanced, mixed technology process that com-

bines precision bipolar circuits with low power CMOS logic.

The part is available in a 24-pin plastic and hermetic

dual-in-line package (DIP) and is also packaged in a 28-termi-

nal plastic leaded chip carrier (PLCC).

1. Complete 14-Bit D/A Function

The AD7840 provides the complete function for creating ac

signals and dc voltages to 14-bit accuracy. The part features

an on-chip reference, an output buffer amplifier and 14-bit

D/A converter.

2. Dynamic Specifications for DSP Users

In addition to traditional dc specifications, the AD7840 is

specified for ac parameters including signal-to-noise ratio and

harmonic distortion. These parameters along with important

timing parameters are tested on every device.

3. Fast, Versatile Microprocessor Interface

The AD7840 is capable of 14-bit parallel and serial interfac-

ing. In the parallel mode, data setup times of 21 ns and write

pulse widths of 45 ns make the AD7840 compatible with

modern 16-bit microprocessors and digital signal processors.

In the serial mode, the part features a high data transfer rate

of 6 MHz.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

AD7840–SPECIFICATIONS

Parameter

DYNAMIC PERFORMANCE

Signal to Noise Ratio

(SNR)

J, A

K, B

–80

Total Harmonic Distortion (THD) –78

Peak Harmonic or Spurious Noise

DC ACCURACY

Resolution

Integral Nonlinearity

Differential Nonlinearity

Bipolar Zero Error

Positive Full Scale Error

Negative Full Scale Error

REFERENCE OUTPUT

REF OUT @ +25°C

REF OUT TC

Reference Load Change

(∆REF OUT vs.

∆I)

REFERENCE INPUT

Reference Input Range

Input Current

LOGIC INPUTS

Input High Voltage, V

INH

Input Low Voltage, V

INL

Input Current, I

Input Current (CS Input Only)

Input Capacitance, C

IN7

ANALOG OUTPUT

Output Voltage Range

DC Output Impedance

Short-Circuit Current

AC CHARACTERISTICS

Voltage Output Settling Time

Positive Full-Scale Change

Negative Full-Scale Change

Digital-to-Analog Glitch Impulse

Digital Feedthrough

POWER REQUIREMENTS

Power Dissipation

–78

= +5 V 5%, V

= –5 V 5%, AGND = DGND = O V, REF IN = +3 V, R

= 2 k ,

= 100 pF. All specifications T

MIN

to T

MAX

unless othewise noted.)

–78

Units

dB min

dB max

Test Conditions/Comments

OUT

= 1 kHz Sine Wave, f

SAMPLE

= 100 kHz

Typically 82 dB at +25°C for 0 < V

OUT

< 20 kHz

OUT

= 1 kHz Sine Wave, f

SAMPLE

= 100 kHz

Typically –84 dB at +25°C for 0 < V

OUT

< 20 kHz

OUT

= 1 kHz Sine Wave, f

SAMPLE

= 100 kHz

Typically –84 dB at +25°C for 0 < V

OUT

< 20 kHz

0.9

2.99

3.01

–1

2.85

3.15

2.4

0.8

0.1

0.9

2.99

3.01

–1

2.85

3.15

2.4

0.8

0.1

0.9

2.99

3.01

–1

2.85

3.15

2.4

0.8

0.1

Bits

LSB max

V min

V max

ppm/°C max

mV max

V min

V max

µA

max

V min

V max

µA

max

µA

max

pF max

V nom

Ω

typ

mA typ

Guaranteed Monotonic

Reference Load Current Change (0–500

µA)

3 V

= 5 V

= 0 V to V

to V

–5

100

–5

100

–5

110

µs

max

µs

max

nV secs typ

V nom

mA max

mW max

Settling Time to within

1/2 LSB of Final Value

Typically 2

µs

Typically 2.5

µs

5% for Specified Performance

Output Unloaded, SCLK = +5 V. Typically 10 mA

Output Unloaded, SCLK = +5 V. Typically 4 mA

Typically 70 mW

NOTES

Temperature ranges are as follows: J, K Versions, 0°C to +70°C; A, B Versions, –25°C to +85°C; S Version, –55°C to +125°C.

OUT

(pk-pk) =

3 V

SNR calculation includes distortion and noise components.

Using external sample-and-hold (see Testing the AD7840).

Measured with respect to REF IN and includes bipolar offset error.

For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).

Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

–2–

REV. B

AD7840

TIMING CHARACTERISTICS

1, 2

Parameter

8 3

Limit at T

MIN

, T

MAX

(J, K, A, B Versions)

150

= +5 V

5%, V

= –5 V

5%, AGND = DGND = 0 V.)

Units

ns min

Conditions/Comments

Setup Time

Hold Time

Pulse Width

Data Valid to

Setup Time

Data Valid to

Hold Time

LDAC

Pulse Width

SYNC

to SCLK Falling Edge

SCLK Cycle Time

Data Valid to SCLK Setup Time

Data Valid to SCLK Hold Time

SYNC

to SCLK Hold Time

Limit at T

MIN

, T

MAX

(S Version)

200

100

NOTES

Timing specifications in

bold print

are 100% production tested. All other times are sample tested at +25

°C

to ensure compliance. All input signals are specified with

tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

See Figures 6 and 8.

SCLK mark/space ratio is 40/60 to 60/40.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

ORDERING GUIDE

Temperature

Range

0°C to +70°C

–25°C to +85°C

–55°C to +125°C

SNR

(dB)

78 min

80 min

78 min

80 min

78 min

80 min

78 min

Integral

Nonlinearity

(LSB)

2 max

1 max

2 max

1 max

2 max

1 max

2 max

Package

Option

N-24

P-28A

Q-24

RS-24

Q-24

Q-2

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

OUT

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V

to V

REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . 0 V to V

REF IN to AGND . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V

+ 0.3 V

Operating Temperature Range

Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C

Industrial (A, B Versions) . . . . . . . . . . . . . . –25°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Model

AD7840JN

AD7840KN

AD7840JP

AD7840KP

AD7840AQ

AD7840ARS

AD7840BQ

AD7840SQ

NOTES

To order MIL-STD-883, Class B processed parts, add /883B to part number.

Contact your local sales office for military data sheet and availability.

N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.

This grade will be available to /883B processing only.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7840 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–3–

AD7840

PIN FUNCTION DESCRIPTION

DIP

No.

Mnemonic

CS/SERIAL

Function

Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used

in conjunction with

to load parallel data to the input latch. For applications where

is perma-

nently low, an R, C is required for correct power-up (see

LDAC

input). If this input is tied to V

, it de-

fines the AD7840 for serial mode operation.

Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with

to load

parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se-

rial data expected after the falling edge of this signal.

Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode,

SDATA is the serial data input which is used in conjunction with

SYNC

and SCLK to transfer serial data

to the AD7840 input latch.

Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is

the serial clock input. Serial data bits are latched on the falling edge of SCLK when

SYNC

is low.

Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic

1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates

that the LSB is the first valid bit (see Table I).

Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode,

this input controls the serial data justification (see Table I).

Data Bit 9 to Data Bit 5. Parallel data inputs.

Digital Ground. Ground reference for digital circuitry.

Data Bit 4 to Data Bit 1. Parallel data inputs.

Data Bit 0 (LSB). Parallel data input.

Positive Supply, +5 V

5%.

Analog Ground. Ground reference for DAC, reference and output buffer amplifier.

Analog Output Voltage. This is the buffer amplifier output voltage. Bipolar output range (± 3 V with REF

IN = +3 V).

Negative Supply Voltage, –5 V

5%.

Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To operate the

AD7840 with internal reference, REF OUT should be connected to REF IN. The external load capability

of the reference is 500

µA.

Voltage Reference Input. The reference voltage for the DAC is applied to this pin. It is internally buffered

before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 is

3 V.

Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling

edge of this signal (see Interface Logic Information section). The AD7840 should be powered-up with

LDAC

high. For applications where

LDAC

is permanently low, an R, C is required for correct power-up

(see Figure 19).

Table I. Serial Data Modes

WR/SYNC

D13/SDATA

D12/SCLK

D11/FORMAT

7–11

13–16

D10/JUSTIFY

D9–D5

DGND

D4–D1

AGND

OUT

REF OUT

REF IN

LDAC

–4–

REV. B

AD7840

PIN CONFIGURATIONS

DIP/SSOP

PLCC

D/A SECTION

The AD7840 contains a 14-bit voltage mode D/A converter

consisting of highly stable thin film resistors and high speed

NMOS single-pole, double-throw switches. The simplified cir-

cuit diagram for the DAC section is shown in Figure 1. The

three MSBs of the data word are decoded to drive the seven

switches A–G. The 11 LSBs switch an 11-bit R-2R ladder struc-

ture. The output voltage from this converter has the same polar-

ity as the reference voltage, REF IN.

The REF IN voltage is internally buffered by a unity gain ampli-

fier before being applied to the D/A converter and the bipolar

bias circuitry. The D/A converter is configured and sealed for a

3 V reference and the device is tested with 3 V applied to REF

IN. Operating the AD7840 at reference voltages outside the

5% tolerance range may result in degraded performance from

the part.

for external use, it should he decoupled to AGND with a 200

Ω

resistor in series with a parallel combination of a 10

µF

tantalum

capacitor and a 0.1

µF

ceramic capacitor.

Figure 2. Internal Reference

EXTERNAL REFERENCE

In some applications, the user may require a system reference or

some other external reference to drive the AD7840 reference in-

put. Figure 3 shows how the AD586 5 V reference can be con-

ditioned to provide the 3 V reference required by the AD7840

REF IN. An alternate source of reference voltage for the

AD7840 in systems which use both a DAC and an ADC is to

use the REF OUT voltage of ADCs such as the AD7870 and

AD7871. A circuit showing this arrangement is shown in

Figure 20.

Figure 1. DAC Ladder Structure

INTERNAL REFERENCE

The AD7840 has an on-chip temperature compensated buried

Zener reference (see Figure 2) which is factory trimmed to 3 V

10 mV. The reference voltage is provided at the REF OUT

pin. This reference can be used to provide both the reference

voltage for the D/A converter and the bipolar bias circuitry. This

is achieved by connecting the REF OUT pin to the REF IN pin

of the device.

The reference voltage can also be used as a reference for other

components and is capable of providing up to 500

µA

to an ex-

ternal load. The maximum recommended capacitance on REF

OUT for normal operation is 50 pF. If the reference is required

REV. B

–5–

Figure 3. AD586 Driving AD7840 REF IN

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AD7840BQ Related Products

	AD7840BQ	AD7840AQ	AD7840KN	AD7840SQ
Description	IC SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24, HERMETIC SEALED, CERDIP-24, Digital to Analog Converter	IC SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, CDIP24, HERMETIC SEALED, CERDIP-24, Digital to Analog Converter	IC SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, PDIP24, PLASTIC, DIP-24, Digital to Analog Converter	IC SERIAL, PARALLEL, WORD INPUT LOADING, 2 us SETTLING TIME, 14-BIT DAC, CDIP24, HERMETIC SEALED, CERDIP-24, Digital to Analog Converter
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Maker	ADI	ADI	ADI	ADI
Parts packaging code	DIP	DIP	DIP	DIP
package instruction	HERMETIC SEALED, CERDIP-24	HERMETIC SEALED, CERDIP-24	PLASTIC, DIP-24	HERMETIC SEALED, CERDIP-24
Contacts	24	24	24	24
Reach Compliance Code	unknown	not_compliant	not_compliant	unknown
ECCN code	EAR99	EAR99	EAR99	3A001.A.2.C
Maximum analog output voltage	3 V	3 V	3 V	3 V
Minimum analog output voltage	-3 V	-3 V	-3 V	-3 V
Converter type	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER	D/A CONVERTER
Enter bit code	2\'S COMPLEMENT BINARY	2\'S COMPLEMENT BINARY	2\'S COMPLEMENT BINARY	BINARY
Input format	SERIAL, PARALLEL, WORD	SERIAL, PARALLEL, WORD	SERIAL, PARALLEL, WORD	SERIAL, PARALLEL, WORD
JESD-30 code	R-GDIP-T24	R-GDIP-T24	R-PDIP-T24	R-GDIP-T24
JESD-609 code	e0	e0	e0	e0
Maximum linear error (EL)	0.0061%	0.0122%	0.0061%	0.0122%
Nominal negative supply voltage	-5 V	-5 V	-5 V	-5 V
Number of digits	14	14	14	14
Number of functions	1	1	1	1
Number of terminals	24	24	24	24
Maximum operating temperature	85 °C	85 °C	70 °C	125 °C
Minimum operating temperature	-25 °C	-25 °C	-	-55 °C
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP24,.3	DIP24,.3	DIP24,.3	DIP24,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT APPLICABLE	NOT SPECIFIED
power supply	+-5 V	+-5 V	+-5 V	+-5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	5.33 mm	5.08 mm
Maximum stabilization time	4 µs	4 µs	4 µs	4 µs
Nominal settling time (tstl)	2.5 µs	2.5 µs	2.5 µs	2 µs
Maximum slew rate	14 mA	14 mA	14 mA	15 mA
Nominal supply voltage	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO
technology	BICMOS	BICMOS	BICMOS	BICMOS
Temperature level	OTHER	OTHER	COMMERCIAL	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT APPLICABLE	NOT SPECIFIED
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm

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