MT9HTF12872CHY-40EE1 datasheet, PDF

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MT9HTF12872CHY-40EE1: DescriptionDDR DRAM Module, 128MX72, CMOS, LEAD FREE, SOCDIMM-200; Categorystorage storage; File Size308KB，22 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT9HTF12872CHY-40EE1 Overview

DDR DRAM Module, 128MX72, CMOS, LEAD FREE, SOCDIMM-200

MT9HTF12872CHY-40EE1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	SODIMM
package instruction	DIMM,
Contacts	200
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XZMA-N200
JESD-609 code	e4
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	200
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	ZIG-ZAG
Maximum time at peak reflow temperature	30

MT9HTF12872CHY-40EE1 Preview

512MB, 1GB (x72, SR) 200-Pin DDR2 SDRAM SOCDIMM

Features

DDR2 SDRAM SOCDIMM

MT9HTF6472CH – 512MB

MT9HTF12872CH – 1GB

For component data sheets, refer to Micron’s Web site:

www.micron.com

Features

• 200-pin, small-outline, clocked, dual in-line memory

module (SOCDIMM)

• Fast data transfer rates: PC2-3200, PC2-4200,

PC2-5300, or PC2-6400

• 512MB (128 Meg x 72), 1GB (256 Meg x 72)

• Supports ECC error detection and correction

• V

= V

Q = +1.8V

• V

DDSPD

= +3.0V to +3.6V

• JEDEC-standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• 4n-bit prefetch architecture

• Multiple internal device banks for concurrent

operation

• Programmable CAS# latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• Phase-lock loop (PLL) to reduce system clock line

• Gold edge contacts

• Single rank

• I

C temperature sensor

Figure 1:

200-Pin SOCDIMM (MO-224 R/C B)

PCB height: 30.0mm (1.18in)

Options

• Operating temperature

–

Commercial (0°C

≤

+70°C)

–

Industrial (–40°C

≤

+85°C)

• Package

–

200-pin DIMM (Pb-free)

• Frequency/CAS latency

–

2.5ns @ CL = 5 (DDR2-800)

–

2.5ns @ CL = 6 (DDR2-800)

–

3.0ns @ CL = 5 (DDR2-667)

–

3.75ns @ CL = 4 (DDR2-533)

–

5.0ns @ CL = 3 (DDR2-400)

• PCB height

–

30.0mm (1.18in)

Marking

None

-80E

-800

-667

-53E

-40E

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. Contact Micron for product availability.

Table 1:

Speed

Grade

-80E

-800

-667

-53E

-40E

Key Timing Parameters

Industry

Nomenclature

PC2-6400

PC2-5300

PC2-4200

PC2-3200

Data Rate (MT/s)

CL = 6

–

800

–

CL = 5

800

667

–

CL = 4

533

400

CL = 3

–

400

RCD

(ns)

12.5

(ns)

12.5

PDF: 09005aef828eddb4/ Source: 09005aef828edcf5

HTF9C64_128x72CH.fm - Rev. A 3/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512MB, 1GB (x72, SR) 200-Pin DDR2 SDRAM SOCDIMM

Features

Table 2:

Address Table

512MB

Refresh count

Row address

Device bank address

Device page size per bank

Device configuration

Column address

Module rank address

16K (A0–A13)

4 (BA0, BA1)

1KB

512Mb (64 Meg x 8)

1K (A0–A9)

1 (S0#)

1GB

16K (A0–A13)

8 (BA0–BA2)

1KB

1Gb (128 Meg x 8)

1K (A0–A9)

1 (S0#)

Table 3:

Part Numbers and Timing Parameters – 512MB Modules

Base device: MT47H64M8,

512Mb DDR2 SDRAM

Module

Density

512MB

Module

Bandwidth

6.4 GB/s

5.3 GB/s

4.3 GB/s

3.2 GB/s

Memory Clock/

Data Rate

2.5ns/800 MT/s

3.0ns/667 MT/s

3.75ns/533 MT/s

5.0ns/400 MT/s

Latency

(CL-

RCD-

RP)

5-5-5

6-6-6

5-5-5

4-4-4

3-3-3

Part Number

MT9HTF6472CHY-80E__

MT9HTF6472CHY-800__

MT9HTF6472CHY-667__

MT9HTF6472CHY-53E__

MT9HTF6472CHY-40E__

Configuration

64 Meg x 72

Table 4:

Part Numbers and Timing Parameters – 1GB Modules

Base device: MT47H128M8,

1Gb DDR2 SDRAM

Module

Density

1GB

Module

Bandwidth

6.4 GB/s

5.3 GB/s

4.3 GB/s

3.2 GB/s

Memory Clock/

Data Rate

2.5ns/800 MT/s

3.0ns/667 MT/s

3.75ns/533 MT/s

5.0ns/400 MT/s

Latency

(CL-

RCD-

RP)

5-5-5

6-6-6

5-5-5

4-4-4

3-3-3

Part Number

MT9HTF12872CHY-80E__

MT9HTF12872CHY-800__

MT9HTF12872CHY-667__

MT9HTF12872CHY-53E__

MT9HTF12872CHY-40E__

Notes:

Configuration

128 Meg x 72

1. Data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown), designating component and PCB

revisions. Consult factory for current revision codes. Example: MT9HTF12872CHY-40EE1.

PDF: 09005aef828eddb4/ Source: 09005aef828edcf5

HTF9C64_128x72CH.fm - Rev. A 3/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MB, 1GB (x72, SR) 200-Pin DDR2 SDRAM SOCDIMM

Pin Assignments and Descriptions

Table 5:

Pin Assignments

200-Pin SOCDIMM Front

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REF

DQ0

DQ1

DQS0#

DQS0

DQ2

DQ3

DQ8

DQ9

DQS1#

DQS1

DQ10

DQ11

DQ16

DQ17

DQS2#

DQS2

DQ18

DQ19

DQ24

DQ25

DQS3#

DQS3

DQ26

DQ27

CB0

CB1

DQS8#

DQS8

CKE0

EVENT#

A12

Notes:

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

A10

BA0

RAS#

CAS#

DQ32

DQ33

DQS4#

DQS4

DQ34

DQ35

DQ40

DQ41

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

DQS5#

DQS5

DQ42

DQ43

DQ48

DQ49

DQS6#

DQS6

DQ50

DQ51

DQ56

DQ57

DQS7#

DQS7

DQ58

DQ59

DDSPD

200-Pin SOCDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

DQ4

DQ5

DM0

DQ6

DQ7

DQ12

DQ13

DM1

DQ14

DQ15

DQ20

DQ21

RESET#

DM2

DQ22

DQ23

100

DQ28

DQ29

DM3

DQ30

DQ31

CB4

CB5

DM8

CB6

CB7

CB2

CB3

NC/BA2

A11

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

140

142

144

146

148

150

BA1

WE#

S0#

ODT0

A13

CK0

CK0#

DQ36

DQ37

DM4

DQ38

DQ39

DQ44

DQ45

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

DM5

DQ46

DQ47

DQ52

DQ53

DM6

DQ54

DQ55

DQ60

DQ61

DM7

DQ62

DQ63

SDA

SCL

SA1

SA0

1. Pin 92 is NC for 512MB, BA2 for 1GB.

PDF: 09005aef828eddb4/ Source: 09005aef828edcf5

HTF9C64_128x72CH.fm - Rev. A 3/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MB, 1GB (x72, SR) 200-Pin DDR2 SDRAM SOCDIMM

Pin Assignments and Descriptions

Table 6:

Pin Descriptions

Type

Input

(SSTL_18)

Description

On-die termination:

ODT (registered HIGH) enables termination resistance internal

to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins:

DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD

MODE command.

Clock:

CK and CK# are differential clock inputs. All address and control input signals

are sampled on the crossing of the positive edge of CK and negative edge of CK#.

Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

Clock enable:

CKE (registered HIGH) activates and CKE (registered LOW) deactivates

clocking circuitry on the DDR2 SDRAM.

Chip select:

S# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when S# is registered HIGH. S# provides for

external rank selection on systems with multiple ranks. S# is considered part of the

command code.

Command inputs:

RAS#, CAS#, and WE# (along with S#) define the command being

entered.

Bank address inputs:

BA0–BA1/BA2 define to which device bank an ACTIVE, READ,

WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode

command.

Address inputs:

Provide the row address for ACTIVE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one device

bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10

HIGH). The address inputs also provide the op-code during a LOAD MODE command.

Input data mask:

DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is

sampled on both edges of DQS. Although DM pins are input-only, the DM loading is

designed to match that of DQ and DQS pins.

Serial clock:

SCL is used to synchronize the presence-detect and temperature sensor

data transfer to and from the module.

Serial address inputs:

These pins are used to configure the presence-detect and

temperature sensor devices.

Disables the output clocks on the PLL when LOW.

Data input/output:

Bidirectional data bus.

Check bits.

Data strobe:

Output with read data, input with write data for source synchronous

operation. Edge-aligned with read data, center-aligned with write data. DQS# is only

used when differential data strobe mode is enabled via the LOAD MODE command.

Serial data:

SDA is a bidirectional pin used to transfer addresses and data into and

out of the presence-detect and temperature sensor devices.

Temperature sensor alarm output.

Power supply:

+1.8V ±0.1V.

SSTL_18 reference voltage.

Ground.

Serial EEPROM and temperature sensor positive power supply:

+3.0V to +3.6V.

No connect:

These pins should be left unconnected.

Symbol

ODT0

CK0, CK0#

Input

(SSTL_18)

Input

(SSTL_18)

Input

(SSTL_18)

CKE0

S0#

RAS#, CAS#, WE#

BA0, BA1

(512MB)

BA0–BA2

(1GB)

A0–A13

Input

(SSTL_18)

Input

(SSTL_18)

Input

(SSTL_18)

DM0–DM8

Input

(SSTL_18)

SCL

SA0–SA1

RESET#

DQ0–DQ63

CB0–CB7

DQS0–DQS8,

(DQS0#–DQS8#)

SDA

EVENT#

REF

DDSPD

Input

(SSTL_18)

Input

(SSTL_18)

Input

(LVCMOS)

I/O

(SSTL_18)

I/O

(SSTL_18)

I/O

(SSTL_18)

I/O

(SSTL_18)

Output

Supply

–

PDF: 09005aef828eddb4/ Source: 09005aef828edcf5

HTF9C64_128x72CH.fm - Rev. A 3/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MB, 1GB (x72, SR) 200-Pin DDR2 SDRAM SOCDIMM

Functional Block Diagram

Figure 2:

Functional Block Diagram

S0#

DQS0#

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS# DQS DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS4#

DQS4

DM4

DM CS# DQS DQS#

DQS1#

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS# DQS DQS#

DQS5#

DQS5

DM5

DM CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U13

U10

DQS2#

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

CS# DQS DQS#

DQS6#

DQS6

DM6

DM CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS3#

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

CS# DQS DQS#

DQS7#

DQS7

DM7

DM CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U12

DQS8#

DQS8

DM8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

CS# DQS DQS#

CK0

CK0#

PLL

RESET#

DDR2 SDRAM x 2

DDR2 SDRAM x 1

DDR2 SDRAM x 2

U11

SPD EEPROM

WP A0

SCL

SA0 SA1 V

SDA

Temp sensor

EVT A0

SA0 SA1 V

EVENT#

BA0–BA1/BA2

A0–A13

RAS#

CAS#

WE#

CKE0

ODT0

BA0–BA1/BA2: DDR2 SDRAM

A0–A13: DDR2 SDRAM

RAS#: DDR2 SDRAM

CAS#: DDR2 SDRAM

WE#: DDR2 SDRAM

CKE0: DDR2 SDRAM

ODT0: DDR2 SDRAM

SDA

DDSPD

REF

SPD EEPROM, temperature sensor

DDR2 SDRAM

PDF: 09005aef828eddb4/ Source: 09005aef828edcf5

HTF9C64_128x72CH.fm - Rev. A 3/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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MT9HTF12872CHY-40EE1 Related Products

	MT9HTF12872CHY-40EE1	MT9HTF6472CHY-40EXX	MT9HTF12872CHY-40EXX
Description	DDR DRAM Module, 128MX72, CMOS, LEAD FREE, SOCDIMM-200	DDR DRAM Module, 64MX72, CMOS, LEAD FREE, SOCDIMM-200	DDR DRAM Module, 128MX72, CMOS, LEAD FREE, SOCDIMM-200
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Maker	Micron Technology	Micron Technology	Micron Technology
Parts packaging code	SODIMM	SODIMM	SODIMM
package instruction	DIMM,	DIMM,	LEAD FREE, SOCDIMM-200
Contacts	200	200	200
Reach Compliance Code	compliant	compliant	compli
ECCN code	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XZMA-N200	R-XZMA-N200	R-XZMA-N200
JESD-609 code	e4	e4	e4
memory density	9663676416 bit	4831838208 bit	9663676416 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	200	200	200
word count	134217728 words	67108864 words	134217728 words
character code	128000000	64000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	128MX72	64MX72	128MX72
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Gold (Au)	Gold (Au)	Gold (Au)
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal location	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG
Maximum time at peak reflow temperature	30	30	30

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