uboot-2011.12 ported to S3C2440 (Sequence 5) - ARM register description

Refer to "Detailed Explanation of ARM Application System Development"

There are three main types of registers R0~R15 in the ARM architecture:

@Ungrouped registers R0～R7

@Group register R8～R14

@PC register R15

Ungrouped registers

The same register name corresponds to only one independent physical register inside the ARM microprocessor.

Group register

Each physical register corresponds to a different processor mode. For R8~R12, each register corresponds to two different physical registers. When using fiq mode, access registers R8_fiq~R12_fiq; when using other modes except fiq mode, access registers R8_usr~R12_usr. For R13 and R14, each register corresponds to 6 different physical registers, one of which is shared by user mode and system mode, and the other 5 physical registers correspond to the other 5 different operating modes.

Register R13

It is often used as a stack pointer in ARM instructions, but this is just a convention.

R14

Also called the Subroutine Link Register or Link Register LR. When the BL subroutine call instruction is executed, R14 gets a copy of R15.

An example of using the R14 register is: when a subroutine is called using the BL or BLX instruction, the current value of the PC is copied to R14. After the subroutine is executed, the value of R14 is copied back to the PC to complete the call and return of the subroutine.

Subroutine return instruction: MOV PC, LR or BX LR

Store R14 on the stack: STMFD SP!,{,LR}

Pop R14 when the subroutine returns: LDMFD SP!, {, PC}

Program counter PC (R15)

In ARM mode, PC bits [1:0] are 0, and bits [31:2] are used to store PC; in Thumb mode, bit [0] is 0, and bits [31:1] are used to store PC. (Complies with the word alignment rules of ARM microprocessors: 32-bit or 16-bit instruction length, and storage is in bytes). For the ARM instruction set, PC always points to the next two instructions of the current instruction. That is, the value of PC is the address value of the current instruction plus 8 bytes.

Register R16

Register R16 is used as the current program status register CPSR

Condition Code Flags

N, Z, C, and V are all conditional code flags. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether an instruction is executed. In ARM state, most instructions are executed conditionally.

When N is used to perform operations on signed numbers represented by two's complement, N=1 indicates that the result of the operation is a negative number; N=0 indicates that the result of the operation is a positive number or zero;

Z Z=1 means the result of the operation is zero; Z=0 means the result of the operation is non-zero;

C can have 4 ways to set the value of C:

─ Addition operation (including comparison instruction CMN): When the operation result produces a carry (unsigned number overflow), C=1, otherwise C=0.

─ Subtraction operation (including comparison instruction CMP): When a borrow occurs during the operation (unsigned overflow), C=0, otherwise C=1.

─ For non-addition/subtraction instructions that include shift operations, C is the last bit of the value shifted out.

─ For other non-addition/subtraction operation instructions, the value of C usually does not change.

There are two ways to set the value of V:

─ For addition/subtraction operation instructions, when the operands and the operation results are signed numbers represented by binary's complement, V=1 indicates sign bit overflow.

─ For other non-addition/subtraction operation instructions, the value of V usually does not change

Control bit

The lower 8 bits of PSR (including I, F, T, and M[4:0]) are called control bits, which can be changed when an exception occurs. If the processor runs in privileged mode, these bits can be modified by the program.

─ Interrupt disable bits I, F: I=1 disables IRQ interrupt; F=1 disables FIQ interrupt.

─ T flag: This bit reflects the running state of the processor. For T series processors of ARM architecture v5 and above, when this bit is 1, the program runs in Thumb state, otherwise it runs in ARM state. For non-T series processors of ARM architecture v5 and above, when this bit is 1, executing the next instruction causes a defined instruction exception, and when this bit is 0, it means running in ARM state.

─ Operation mode bits M[4:0]: M0, M1, M2, M3, M4 are mode bits. These bits determine the operation mode of the processor.

Reserved bits

SPSR

Each operating mode has a dedicated physical status register called SPSR (Saved Program Status Register). When an exception occurs, SPSR is used to save the current value of CPSR, and SPSR can restore CPSR when exiting from the exception.

Since user mode and system mode are not exception modes, they do not have SPSR. When accessing SPSR in these two modes, the result is unknown.