W49F201T-55 datasheet, PDF - EEWORLD Datasheet

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W49F201T-55: Description128K X 16 CMOS FLASH MEMORY; Categorystorage storage; File Size176KB，23 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W49F201T-55 Overview

128K X 16 CMOS FLASH MEMORY

W49F201T-55 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Winbond Electronics Corporation
Parts packaging code	TSOP
package instruction	12 X 20 MM, TSOP-48
Contacts	48
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	55 ns
startup block	BOTTOM
command user interface	YES
Data polling	YES
JESD-30 code	R-PDSO-G48
JESD-609 code	e0
length	18.4 mm
memory density	2097152 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	3,1
Number of terminals	48
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	8K,104K
Maximum standby current	0.0001 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	12 mm

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Preliminary W49F201

128K

16 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K

16 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

not required. The unique cell architecture of the W49F201 results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt operations:

−

5-volt Read/Erase/Program

Fast Program operation:

−

Word-by-Word programming: 50

µS

(max.)

Fast Erase operation: 60 mS (typ.)

Fast Read access time: 45/55 nS

Endurance: 1K/10K cycles (typ.)

Ten-year data retention

Hardware data protection

Sector configuration

−

One 8K words boot block with lockout

protection

−

Two 8K words parameter blocks

−

One 104K words (208K bytes) Main Memory

Array Blocks

•

Low power consumption

−

Active current: 25 mA (typ.)

−

Standby current: 20

µA

(typ.)

•

Automatic program and erase timing with

internal V

generation

End of program or erase detection

−

Toggle bit

−

Data polling

•

Latched address and data

TTL compatible I/O

JEDEC standard word-wide pinouts

Available packages: 44-pin SOP, 48-pin TSOP

-1-

Publication Release Date: June 1999

Revision A1

Preliminary W49F201

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for

the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer

to the timing waveforms for further details.

Reset Operation

The RESET input pin can be used in some application. When RESET pin is at high state, the device

is in normal operation mode. When RESET pin is driven low for at least a period of T

, it will halts

the device and all outputs are at high impedance state. The device also resets the internal state

machine to read array data. The operation that was interrupted should be reinitiated once the device

is ready to accept another command sequence to assure data integrity. As the high state re-asserted

to the RESET pin, the device will return to read or standby mode, it depends on the control signals.

The system can read data T

after the RESET pin returns to V

. The other function for RESET pin

is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be

reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in

the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set

the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed by the regular programming method.

There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the

lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once

the RESET pin returns to TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform

software command sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address "0002

hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the

output data in DQ0 is "0",

the lockout feature is inactivated and the block can be

erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be

Publication Release Date: June 1999

Revision A1

-3-

Preliminary W49F201

completed in a fast 100 mS (typical). The host system is not required to provide any control or timing

during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation

if the boot block programming lockout feature is not activated. Once the boot block lockout feature is

activated, the chip erase function will erase all the sectors except the boot mode.

Sector Erase Operation

The three sectors, main memory and two parameters blocks, can be erased individually by initiating a

six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle

while the 30(hex) data input command is latched at the rising edge of WE. After the command

loading cycle, the device enters the internal sector erase mode, which is automatically timed and will

be completed in a fast 100 mS (typical). The host system is not required to provide any control or

timing during this operation. The device will automatically return to normal read mode after the erase

operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

When the boot block lockout feature is inactivated, the boot block and the main memory block will be

erased together. Once the boot block is locked, only the main memory block will be erased by the

execution of sector erase operation.

Program Operation

The W49F201 is programmed on a word-by-word basis. Program operation can only change logical

data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot

block from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word

Programming). The device will internally enter the program operation immediately after the word-

program command is entered. The internal program timer will automatically time-out (50

µS

max. -

) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to

detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F201 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation is inhibited when V

is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When

the W49F201 is in the internal program or erase cycle, any attempt to read DQ

of the last word

loaded will receive the complement of the true data. Once the program or erase cycle is completed,

will show the true data. Note that DQ

will show logical "0" during the erase cycle, and become

logical "1" or true data when the erase cycle has been completed.

-4-

W49F201T-55 Related Products

	W49F201T-55	W49F201T-55B	W49F201T-45B	W49F201T-45	W49F201
Description	128K X 16 CMOS FLASH MEMORY	128K X 16 CMOS FLASH MEMORY	128K X 16 CMOS FLASH MEMORY	128K X 16 CMOS FLASH MEMORY	128K X 16 CMOS FLASH MEMORY
Is it Rohs certified?	incompatible	-	incompatible	incompatible	-
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	-
Parts packaging code	TSOP	TSOP	TSOP	TSOP	-
package instruction	12 X 20 MM, TSOP-48	TSOP1, TSSOP48,.8,20	12 X 20 MM, TSOP-48	12 X 20 MM, TSOP-48	-
Contacts	48	48	48	48	-
Reach Compliance Code	_compli	unknow	_compli	_compli	-
ECCN code	EAR99	EAR99	EAR99	EAR99	-
Maximum access time	55 ns	55 ns	45 ns	45 ns	-
startup block	BOTTOM	BOTTOM	BOTTOM	BOTTOM	-
command user interface	YES	YES	YES	YES	-
Data polling	YES	YES	YES	YES	-
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	-
JESD-609 code	e0	e3	e0	e0	-
length	18.4 mm	18.4 mm	18.4 mm	18.4 mm	-
memory density	2097152 bi	2097152 bi	2097152 bi	2097152 bi	-
Memory IC Type	FLASH	FLASH	FLASH	FLASH	-
memory width	16	16	16	16	-
Number of functions	1	1	1	1	-
Number of departments/size	3,1	3,1	3,1	3,1	-
Number of terminals	48	48	48	48	-
word count	131072 words	131072 words	131072 words	131072 words	-
character code	128000	128000	128000	128000	-
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	-
organize	128KX16	128KX16	128KX16	128KX16	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	TSOP1	TSOP1	TSOP1	TSOP1	-
Encapsulate equivalent code	TSSOP48,.8,20	TSSOP48,.8,20	TSSOP48,.8,20	TSSOP48,.8,20	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	-
power supply	5 V	5 V	5 V	5 V	-
Programming voltage	5 V	5 V	5 V	5 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	-
Department size	8K,104K	8K,104K	8K,104K	8K,104K	-
Maximum standby current	0.0001 A	0.0001 A	0.0001 A	0.0001 A	-
Maximum slew rate	0.05 mA	0.05 mA	0.05 mA	0.05 mA	-
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	-
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	-
surface mount	YES	YES	YES	YES	-
technology	CMOS	CMOS	CMOS	CMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	-
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	-
Terminal location	DUAL	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	-
switch bit	YES	YES	YES	YES	-
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	-
width	12 mm	12 mm	12 mm	12 mm	-

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