A Compromise Method for Low Electromagnetic Interference Design in Power Modules

Even the design of ordinary DC to DC switching converters in power supply design will have a series of problems, especially in high-power power supply design. In addition to functional considerations, engineers must ensure the robustness of the design to meet cost targets, thermal performance and space constraints, and of course, to ensure the design schedule. In addition, for product specifications and system performance considerations, the electromagnetic interference (EMI) generated by the power supply must be low enough. However, the electromagnetic interference level of the power supply is the most difficult item to accurately predict in the design. Some people even think that this is simply impossible. The best that designers can do is to take it into full consideration in the design, especially during layout.

Although the principles discussed in this article apply to a wide range of power supply designs, we will focus only on DC-to-DC converters because they are widely used and almost every hardware engineer will be exposed to work related to them and may have to design a power converter at some point. In this article, we will consider two common trade-offs related to low EMI design; thermal performance, EMI, and solution size related to PCB layout and EMI. In this article, we will use a simple buck converter as an example, as shown in Figure 1.

Figure 1. A typical buck converter.

Measuring radiated and conducted EMI in the frequency domain is a Fourier series expansion of a known waveform. In this article, we focus on radiated EMI performance. In a synchronous buck converter, the main switching waveforms that cause EMI are generated by Q1 and Q2, that is, the current di/dt from drain to source of each FET during its respective conduction cycle. The current waveforms (Q and Q2on) shown in Figure 2 are not very regular trapezoids, but we have more freedom of operation because the transition of the conductor current is relatively slow, so we can apply Formula 1 from Henry Ott's classic book "Noise Reduction Techniques in Electronic Systems". We found that for a similar waveform, its rise and fall time will directly affect the harmonic amplitude or Fourier coefficient (In).

Figure 2. Waveforms of Q1 and Q2

In=2IdSin(nπd)/nπd ×Sin(nπtr/T)/nπtr/T (1)

Where n is the harmonic order, T is the period, I is the peak current intensity of the waveform, d is the duty cycle, and tr is the minimum value of tr or tf.

In practical applications, it is very likely that both odd and even harmonic emissions will be encountered. If only odd harmonics are generated, the duty cycle of the waveform must be exactly 50%. However, such duty cycle accuracy is rarely achieved in practice.

The magnitude of the EMI of the harmonic series is affected by the switching of Q1 and Q2. This can be clearly seen when measuring the rise time tr and fall time tf of the drain-source voltage VDS, or the rate of rise di/dt of the current flowing through Q1 and Q2. This also means that we can simply reduce the EMI level by slowing down the switching speed of Q1 or Q2. This is indeed the case. Extending the switching time does have a great impact on harmonics with frequencies higher than f=1/πtr. However, a compromise must be made between increasing heat dissipation and reducing losses. Nevertheless, it is still a good idea to control these parameters, which helps to strike a balance between EMI and thermal performance. This can be achieved by adding a small resistance (usually less than 5Ω) in series with the gate of Q1 and Q2 to control tr and tf. You can also add a "turn-off diode" in series with the gate resistor to independently control the transition time tr or tf (see Figure 3). This is actually an iterative process, and even the most experienced power supply designers use this method. The ultimate goal is to reduce EMI to acceptable levels by slowing down the switching of transistors while keeping their temperatures low enough to ensure stability.