APPLICATION NOTES
CURRENT LIMITING:
INPUT CAPACITOR SELECTION:
The MSK 5041 has an internal high frequency ceramic ca-
pacitor (0.1uF) between V
IN
and GND. Connect a low-ESR
bulk capacitor directly to the input pin of the MSK 5041. Se-
lect the bulk input filter capacitor according to input ripple-
current requirements and voltage rating, rather than capacitor
value. Electrolytic capacitors that have low enough ESR to
meet the ripple-current requirement invariably have more than
adequate capacitance values. Aluminum-electrolytic capaci-
tors are preferred over tantalum types, which could cause power-
up surge-current failure when connecting to robust AC adapt-
ers or low-impedance batteries. RMS input ripple current is
determined by the input voltage and load current, with the
worst possible case occuring at V
IN
= 2 x V
OUT
:
I
RMS
= I
LOAD
X
√V
OUT
(V
IN
-V
OUT
)
V
IN
The MSK 5041 is equipped with a pair of sense pins that
are used to sense the load current using an external resistor
(Rs). The current-limit circuit resets the main PWM latch and
turns off the internal high-side MOSFET switch whenever the
voltage difference between Sense High and Sense Low ex-
ceeds 100mV. This limiting occurs in both current flow direc-
tions, putting the threshold limit at ±100mV. The tolerance
on the positive current limit is ±20%. The external low-value
sense resistor must be sized for 80mV/Rs to guarantee enough
load capacity. Load components must be designed to with-
stand continuous current stresses of 120mV/Rs.
For very high-current applications, it may be useful to wire
the sense inputs with a twisted pair instead of PCB traces.
This twisted pair needn't be anything unique, perhaps two pieces
of wire-wrap wire twisted together. Low inductance current
sense resistors, such as metal film surface mount styles are
best.
SOFT START/Cton:
OUTPUT CAPACITOR SELECTION:
The output capacitor values are generally determined by
the ESR and voltage rating requirements rather than capaci-
tance requirements for stability. Low ESR capacitors that meet
the ESR requirement usually have more output capacitance than
required for stability. Only specialized low-ESR capacitors in-
tended for switching-regulator applications, such as AVX TPS,
Sprague 595D, Sanyo OS-CON, Nichicon PL series or Kemet
T510 series should be used. The capacitor must meet mini-
mum capacitance and maximum ESR values as given in the
following equations:
C
F
> 2.5V(1 + V
OUT
/V
IN(MIN)
)
V
OUT
x R
SENSE
x f
R
ESR
< R
SENSE
x V
OUT
2.5V
These equations provide 45 degrees of phase margin to
ensure jitter-free fixed-frequency operation and provide a damped
output response for zero to full-load step charges. Lower qual-
ity capacitors can be used if the load lacks large step charges.
Bench testing over temperature is recommended to verify ac-
ceptable noise and transient response. As phase margin is
reduced, the first symptom is timing jitter, which shows up in
the switching waveforms. Technically speaking, this typically
harmless jitter is unstable operation, since the swithcing fre-
quency is non-constant. As the capacitor ESR is increased,
the jitter becomes worse. Eventually, the load-transient wave-
form has enough ringing on it that the peak noise levels exceed
the output voltage tolerance. With zero phase margin and in-
stability present, the output voltage noise never gets much
worse than I
PEAK
x R
ESR
(under constant loads). Designers of
industrial temperature range digital systems can usually multi-
ply the calculated ESR value by a factor of 1.5 without hurting
stability or transient response.
The output ripple is usually dominated by the ESR of the
filter capacitors and can be approximated as I
RIPPLE
x R
ESR
.
Including the capacitive term, the full equation for ripple in the
continuous mode is V
NOISE(p-p)
=I
RIPPLE
x (R
ESR
+ 1/(2πfC)). In
idle mode, the inductor current becomes discontinuous with
high peaks and widely spaced pulses, so the noise can actually
be higher at light load compared to full load. In idle mode, the
output ripple can be calculated as follows:
V
NOISE(p-p)
= 0.02 x R
ESR
+ 0.0003 x 2.35µH x [1/V
OUT
+ 1/(V
IN
-V
OUT
)]
R
SENSE
(R
SENSE
)² x C
The internal soft-start circuitry allows a gradual increase of
the internal current-limit level at start-up for the purpose of
reducing input surge currents, and possibly for power-supply
sequencing. In Disable mode, the soft-start circuit holds the
Cton capacitor discharged to ground. When Enable goes high,
a 4µA current source charges the Cton capacitor up to 3.2V.
The resulting linear ramp causes the internal current-limit thresh-
old to increase proportionally from 20mV to 100mV. The out-
put capacitors charge up relatively slowly, depending on the
Cton capacitor value. The exact time of the output rise de-
pends on output capacitance and load current and is typically
1mS per nanofarad of soft-start capacitance. With no capaci-
tor connected, maximum current limit is reached typically within
10µS.
The MSK 5041 is enabled by applying a logic level high to
the Enable pin. A logic level low will disable the device and
quiescent input current will reduce to approximately 2mA. The
Enable threshold voltage is 1V. If automatic start up is re-
quired, simply connect the pin to V
IN
. Maximum Enable volt-
age is +36V.
ENABLE FUNCTION:
POWER DISSIPATION:
In high current applications, it is very important to ensure
that both MOSFETS are within their maximum junction tem-
perature at high ambient temperatures. Temperature rise can
be calculated based on package thermal resistance and worst
case dissipation for each MOSFET. These worst case dissipa-
tions occur at minimum voltage for the high side MOSFET and
at maximum voltage for the low side MOSFET.
Calculate power dissipation using the following formulas:
Pd (upper FET)=I
LOAD
² x 0.022Ω x DUTY
+ V
IN
x I
LOAD
x f x V
IN
x C
RSS
+20ns
I
GATE
Pd (lower FET)=I
LOAD
² x 0.022Ω x (1-DUTY)
DUTY= (V
OUT
+V
Q2
)
(V
IN
-V
Q1
)
Where: V
Q1
or V
Q2
(on state voltage drop)=I
LOAD
x 0.022Ω
C
RSS
=94pF
I
GATE
=1A
During output short circuit, Q2, the synchronous-rectifier
MOSFET, will have an increased duty factor and will see addi-
tional stress. This can be calculated by:
Q2 DUTY=1-
V
Q2
V
IN(MAX)
-V
Q1
Where: V
Q1
or V
Q2
=(120
MV
/R
SENSE
)x0.022
3
PRELIMINARY Rev. - 6/01